參數(shù)資料
型號(hào): MCP2510-I/P
廠商: Microchip Technology
文件頁(yè)數(shù): 58/80頁(yè)
文件大小: 0K
描述: IC CAN CONTRLER IND TEMP 18DIP
產(chǎn)品培訓(xùn)模塊: CAN Bus Protection
標(biāo)準(zhǔn)包裝: 25
控制器類型: CAN 接口
接口: SPI
電源電壓: 3 V ~ 5.5 V
電流 - 電源: 10mA
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 18-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 18-PDIP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 685 (CN2011-ZH PDF)
配用: DV251001-ND - KIT DEVELOPMENT CAN MCP2510
其它名稱: Q731310
2009 Microchip Technology Inc.
DS39637D-page 61
PIC18F2480/2580/4480/4580
TXB2D6
2480 2580 4480 4580
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TXB2D5
2480 2580 4480 4580
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0uuu uuuu
TXB2D4
2480 2580 4480 4580
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0uuu uuuu
TXB2D3
2480 2580 4480 4580
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0uuu uuuu
TXB2D2
2480 2580 4480 4580
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0uuu uuuu
TXB2D1
2480 2580 4480 4580
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0uuu uuuu
TXB2D0
2480 2580 4480 4580
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0uuu uuuu
TXB2DLC
2480 2580 4480 4580
-x-- xxxx
-u-- uuuu
TXB2EIDL
2480 2580 4480 4580
xxxx xxxx
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TXB2EIDH
2480 2580 4480 4580
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TXB2SIDL
2480 2580 4480 4580
xxxx x-xx
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-uuu uuuu
TXB2SIDH
2480 2580 4480 4580
xxx- x-xx
uuu- u-uu
TXB2CON
2480 2580 4480 4580
0000 0-00
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RXM1EIDL
2480 2580 4480 4580
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RXM1EIDH
2480 2580 4480 4580
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RXM1SIDL
2480 2580 4480 4580
xxx- x-xx
uuu- u-uu
RXM1SIDH
2480 2580 4480 4580
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RXM0EIDL
2480 2580 4480 4580
xxxx xxxx
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RXM0EIDH
2480 2580 4480 4580
xxxx xxxx
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RXM0SIDL
2480 2580 4480 4580
xxx- x-xx
uuu- u-uu
RXM0SIDH
2480 2580 4480 4580
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RXF5EIDL
2480 2580 4480 4580
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RXF5EIDH
2480 2580 4480 4580
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RXF5SIDL
2480 2580 4480 4580
xxx- x-xx
uuu- u-uu
RXF5SIDH
2480 2580 4480 4580
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RXF4EIDL
2480 2580 4480 4580
xxxx xxxx
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RXF4EIDH
2480 2580 4480 4580
xxxx xxxx
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RXF4SIDL
2480 2580 4480 4580
xxx- x-xx
uuu- u-uu
RXF4SIDH
2480 2580 4480 4580
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RXF3EIDL
2480 2580 4480 4580
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RXF3EIDH
2480 2580 4480 4580
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TABLE 5-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1:
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4:
See Table 5-3 for Reset value for specific condition.
5:
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6:
This register reads all ‘0’s until ECAN technology is set up in Mode 1 or Mode 2.
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