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參數(shù)資料
| 型號： | MCM69R618 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 1M Synchronous Late Write Fast SRAM(1M位同步遲寫、快速靜態(tài)RAM) |
| 中文描述： | 100萬同步后寫入快速靜態(tài)存儲器（100萬位同步遲寫，快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 141K |
| 代理商： | MCM69R618 |
MCM69R536
MCM69R618
8
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(0
°
C
≤
TA
≤
70
°
C, Unless Otherwise Noted)
Input Pulse Levels
Input Rise/Fall Time
Input Timing Measurement Reference Level
0.25 to 1.25 V
1 V/ns (20% to 80%)
. . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
0.75 V
Output Timing Reference Level
Clock Input Timing Reference Level
ZQ for 50
Impedance
0.75 V
. . . . . . . . . . . . . . . . . . . . . . . . .
Differential Cross–Point
. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
250
READ/WRITE CYCLE TIMING
(See Note 1)
MCM69R536–5
MCM69R618–5
MCM69R536–6
MCM69R618–6
MCM69R536–7
MCM69R618–7
MCM69R536–8
MCM69R618–8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Cycle Time
tKHKH
tKHKL
tKLKH
tKHQX1
tKHQV
tKHQX
tKHQZ
tGLQX
5
—
6
—
7
—
8
—
ns
Clock High Pulse Width
2
—
2.4
—
2.8
—
3.2
—
ns
Clock Low Pulse Width
2
—
2.4
—
2.8
—
3.2
—
ns
Clock High to Output Low–Z
1
—
1
—
1
—
1
—
ns
2, 3
Clock High to Output Valid
—
2.5
—
3
—
3.5
—
4
ns
Clock High to Output Hold
0.5
—
0.5
—
0.5
—
0.5
—
ns
2
Clock High to Output High–Z
—
2.5
—
3
—
3.5
—
4
ns
2, 3
Output Enable Low to Output
Low–Z
0.5
—
0.5
—
0.5
—
0.5
—
ns
Output Enable Low to Output
Valid
tGLQV
—
2.5
—
3
—
3.5
—
4
ns
Output Enable to Output Hold
tGHQX
tGHQZ
0.5
—
0.5
—
0.5
—
0.5
—
ns
Output Enable High to Output
High–Z
—
2.5
—
3
—
3.5
—
4
ns
2, 3
Setup Times:
Address
Data In
Chip Select
Write Enable
tAVKH
tDVKH
tSVKH
tWVKH
tKHAX
tKHDX
tKHSX
tKHWX
0.5
—
0.5
—
0.5
—
0.5
—
ns
Hold Times:
Address
Data In
Chip Select
Write Enable
1
—
1
—
1
—
1
—
ns
NOTES:
1. In no case may control input signals (e.g., SS) be operated with pulse widths less than the minimum clock input pulse width specifications
(e.g., tKHKL) or at frequencies that exceed the applied K clock frequency.
2. This parameter is sampled and not 100% tested.
3. Measured at
±
200 mV from steady state.
AC INPUT CHARACTERISTICS
Parameter
Symbol
Min
Max
Note
AC Input Logic High (See Figure 4)
VIH (ac)
Vref + 200 mV
—
AC Input Logic Low (See Figure 2 and 4)
VIL (ac)
—
Vref – 200 mV
1
Input Reference Peak to Peak ac Voltage
Vref (ac)
—
5% Vref (dc)
2
Clock Input Differential Voltage
Vdif (ac)
400 mV
VDDQ + 600 mV
3
NOTES:
1. Inputs may undershoot to – 0.5 V (peak) for up to 20% tKHKH (e.g., 2 ns at a clock cycle time of 10 ns).
2. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak to peak ac component
superimposed on Vref may not exceed 5% of the dc component of Vref.
3. Minimum differential input voltage required for differential input clock operation.
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