- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369915 > MCM69R618 (Motorola, Inc.) 1M Synchronous Late Write Fast SRAM(1M位同步遲寫、快速靜態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號： | MCM69R618 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 1M Synchronous Late Write Fast SRAM(1M位同步遲寫、快速靜態(tài)RAM) |
| 中文描述： | 100萬同步后寫入快速靜態(tài)存儲器（100萬位同步遲寫，快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 13/20頁 |
| 文件大小： | 141K |
| 代理商： | MCM69R618 |
MCM69R536
MCM69R618
13
MOTOROLA FAST SRAM
SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION
OVERVIEW
The serial boundary scan test access port (TAP) on this
RAM is designed to operate in a manner consistent with
IEEE Standard 1149.1–1990 (commonly referred to as
JTAG), but does not implement all of the functions required
for 1149.1 compliance. Certain functions have been modified
or eliminated because their implementation places extra de-
lays in the RAMs critical speed path. Nevertheless, the RAM
supports the standard TAP controller architecture. (The TAP
controller is the state machine that controls the TAPs opera-
tion) and can be expected to function in a manner that does
not conflict with the operation of devices with Standard
1149.1 compliant TAPs. The TAP operates using convention-
al JEDEC Standard 8–1B Low Voltage (3.3 V) TTL/CMOS
logic level signaling.
DISABLING THE TEST ACCESS PORT
It is possible to use this device without utilizing the TAP. To
disable the TAP Controller without interfering with normal op-
eration of the device, TCK must be tied to VSS to preclude
mid level inputs. TDI and TMS are designed so an undriven
input will produce a response identical to the application of a
logic 1, and may be left unconnected. But they may also be
tied to VDD through a 1 k resistor. TDO should be left uncon-
nected.
TAP DC OPERATING CHARACTERISTICS
(0
°
C
≤
TA
≤
70
°
C, Unless Otherwise Noted)
Parameter
Symbol
Min
Max
Unit
Note
Logic Input Logic High
VIH1
2.0
VDD + 0.3
V
Logic Input Logic Low
VIL1
– 0.3
0.8
V
Logic Input Leakage Current
Ilkg
—
±
5
μ
A
1
Output Logic Low
VOL1
—
0.2
V
2
Output Logic High
VOH1
VDD – 0.2
—
V
3
Output Logic Low
VOL2
—
0.4
V
4
Output Logic High
VOH2
2.4
—
V
5
NOTES:
1. 0 V
≤
Vin
≤
VDD for all logic input pins.
2. IOL1
≤
100
μ
A @ VOL = 0.2 V. Sampled, not 100% tested.
3. |IOH1|
≤
100
μ
A @ VDDQ – 0.2 V. Sampled, not 100% tested.
4. IOL2
≤
8 mA @ VOL = 0.4 V.
5. |IOH2|
≤
8 mA @ VOH = 2.4 V.
相關PDF資料 |
PDF描述 |
|---|---|
| MCM69R536 | 1M Synchronous Late Write Fast SRAM(1M位同步遲寫、快速靜態(tài)RAM) |
| MCT2E | 6-Pin DIP Optoisolators Transistor Output |
| MCT2E | Industry Standard Single Channel 6 Pin DIP Optocoupler |
| MCT2E | PHOTOTRANSISTOR OPTOCOUPLERS |
| MCT2E | PHOTOTRANSISTOR OPTOCOUPLER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MCM69R736A | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69R736AZP5 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69R736AZP5R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69R736AZP6 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69R736AZP6R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
發(fā)布緊急采購，3分鐘左右您將得到回復。