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參數(shù)資料
| 型號(hào)： | MCM69R618 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 1M Synchronous Late Write Fast SRAM(1M位同步遲寫、快速靜態(tài)RAM) |
| 中文描述： | 100萬同步后寫入快速靜態(tài)存儲(chǔ)器（100萬位同步遲寫，快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 141K |
| 代理商： | MCM69R618 |
MCM69R536
MCM69R618
1
Motorola, Inc. 1997
Advance Information
1M Late Write HSTL
The MCM69R536/618 is a 1 megabit synchronous late write fast static RAM
designed to provide high performance in secondary cache, ATM switch,
Telecom, and other high speed memory applications. The MCM69R618
organized as 64K words by 18 bits, and the MCM69R536 organized as 32K
words by 36 bits wide are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
The differential CK clock inputs control the timing of read/write operations of
the RAM. At the rising edge of the CK clock all addresses, write enables, and
synchronous selects are registered. An internal buffer and special logic enable
the memory to accept write data on the rising edge of the CK clock a cycle after
address and control signals. Read data is driven on the rising edge of the CK
clock also.
The RAM uses HSTL inputs and outputs. The adjustable input trip – point (Vref)
and output voltage (VDDQ) gives the system designer greater flexibility in
optimizing system performance.
The synchronous write and byte enables allow writing to individual bytes or the
entire word.
The impedance of the output buffers is programmable allowing the outputs to
match the impedance of the circuit traces which reduces signal reflections.
Byte Write Control
Single 3.3 V + 10%, – 5% Operation
HSTL – I/O (JEDEC Standard JESD8–6 Class 1 Compatible)
HSTL – User Selectable Input Trip–Point
HSTL – Compatible Programmable Impedance Output Drivers
Register to Register Synchronous Operation
Asynchronous Output Enable
Boundary Scan (JTAG) IEEE 1149.1 Compatible
Differential Clock Inputs
Optional x18 or x36 organization
MCM69R536/618–5 = 5 ns
MCM69R536/618–6 = 6 ns
MCM69R536/618–7 = 7 ns
MCM69R536/618–8 = 8 ns
119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array
(PBGA) Package
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Order this document
by MCM69R536/D
SEMICONDUCTOR TECHNICAL DATA
MCM69R536
MCM69R618
ZP PACKAGE
PBGA
CASE 999–01
REV 1
8/15/97
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| MCM69R536 | 1M Synchronous Late Write Fast SRAM(1M位同步遲寫、快速靜態(tài)RAM) |
| MCT2E | 6-Pin DIP Optoisolators Transistor Output |
| MCT2E | Industry Standard Single Channel 6 Pin DIP Optocoupler |
| MCT2E | PHOTOTRANSISTOR OPTOCOUPLERS |
| MCT2E | PHOTOTRANSISTOR OPTOCOUPLER |
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| MCM69R736A | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69R736AZP5 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69R736AZP5R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69R736AZP6 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69R736AZP6R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
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