• 參數(shù)資料
    型號: MCIMX357DJQ5CR2
    廠商: Freescale Semiconductor
    文件頁數(shù): 4/147頁
    文件大?。?/td> 0K
    描述: MULTIMEDIA PROCESSOR 400-MAPBGA
    標準包裝: 1,000
    系列: i.MX35
    核心處理器: ARM11
    芯體尺寸: 32-位
    速度: 532MHz
    連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSI,UART/USART,USB OTG
    外圍設備: DMA,I²S,LCD,POR,PWM,WDT
    輸入/輸出數(shù): 96
    程序存儲器類型: ROMless
    RAM 容量: 128K x 8
    電壓 - 電源 (Vcc/Vdd): 1.33 V ~ 1.47 V
    振蕩器型: 外部
    工作溫度: -20°C ~ 70°C
    封裝/外殼: 400-LFBGA
    包裝: 帶卷 (TR)
    i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
    Freescale Semiconductor
    101
    ata_buffer_en is negated, the bus drives from device to host. Steering of the signal is such that contention
    on the host and device tri-state buses is always avoided.
    4.9.17.3
    Timing Parameters
    Table 68 shows the parameters used in the timing equations. These parameters depend on the
    implementation of the ATA interface on silicon, the bus buffer used, the cable delay, and the cable skew.
    Table 68. ATA Timing Parameters
    Name
    Description
    Value/
    Contributing Factor1
    1 Values provided where applicable.
    T
    Bus clock period (ipg_clk_ata)
    Peripheral clock
    frequency
    ti_ds
    Set-up time ata_data to ata_iordy edge (UDMA-in only)
    UDMA0
    UDMA1
    UDMA2, UDMA3
    UDMA4
    UDMA5
    15 ns
    10 ns
    7ns
    5ns
    4ns
    ti_dh
    Hold time ata_iordy edge to ata_data (UDMA-in only)
    UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
    UDMA5
    5.0 ns
    4.6 ns
    tco
    Propagation delay bus clock L-to-H to
    ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data,
    ata_buffer_en
    12.0 ns
    tsu
    Set-up time ata_data to bus clock L-to-H
    8.5 ns
    tsui
    Set-up time ata_iordy to bus clock H-to-L
    8.5 ns
    thi
    Hold time ata_iordy to bus clock H to L
    2.5 ns
    tskew1 Maximum difference in propagation delay bus clock L-to-H to any of following signals
    ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
    (write), ata_buffer_en
    7ns
    tskew2 Maximum difference in buffer propagation delay for any of following signals
    ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
    (write), ata_buffer_en
    Transceiver
    tskew3 Maximum difference in buffer propagation delay for any of following signals ata_iordy,
    ata_data (read)
    Transceiver
    tbuf
    Maximum buffer propagation delay
    Transceiver
    tcable1 Cable propagation delay for ata_data
    Cable
    tcable2 Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack
    Cable
    tskew4 Maximum difference in cable propagation delay between ata_iordy and ata_data (read)
    Cable
    tskew5 Maximum difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack)
    and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
    Cable
    tskew6 Maximum difference in cable propagation delay without accounting for ground bounce
    Cable
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