參數(shù)資料
型號(hào): MCIMX357DJQ5CR2
廠商: Freescale Semiconductor
文件頁數(shù): 108/147頁
文件大小: 0K
描述: MULTIMEDIA PROCESSOR 400-MAPBGA
標(biāo)準(zhǔn)包裝: 1,000
系列: i.MX35
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲(chǔ)器類型: ROMless
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.33 V ~ 1.47 V
振蕩器型: 外部
工作溫度: -20°C ~ 70°C
封裝/外殼: 400-LFBGA
包裝: 帶卷 (TR)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
63
Figure 41 shows MII asynchronous input timings listed in Table 50.
Figure 41. MII Asynch Inputs Timing Diagram
4.9.8.5
MII Serial Management Channel Timing
Serial management channel timing is accomplished using FEC_MDIO and FEC_MDC. The FEC
functions correctly with a maximum MDC frequency of 2.5 MHz. Table 51 lists MII serial management
channel timings.
The MDC frequency should be equal to or less than 2.5 MHz to be compliant with the IEEE 802.3 MII
specification. However the FEC can function correctly with a maximum MDC frequency of 15 MHz.
Table 51. MII Transmit Signal Timing
Num
Characteristic
Min.
Max.
Units
M10
FEC_MDC falling edge to FEC_MDIO output invalid (minimum
propagation delay)
0—
ns
M11
FEC_MDC falling edge to FEC_MDIO output valid (max.
propagation delay)
—5
ns
M12
FEC_MDIO (input) to FEC_MDC rising edge setup
18
ns
M13
FEC_MDIO (input) to FEC_MDC rising edge hold
0
ns
M14
FEC_MDC pulse width high
40%
60%
FEC_MDC period
M15
FEC_MDC pulse width low
40%
60%
FEC_MDC period
FEC_CRS, FEC_COL
M9
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