參數(shù)資料
型號: MCIMX357DJQ5CR2
廠商: Freescale Semiconductor
文件頁數(shù): 145/147頁
文件大小: 0K
描述: MULTIMEDIA PROCESSOR 400-MAPBGA
標(biāo)準(zhǔn)包裝: 1,000
系列: i.MX35
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲器類型: ROMless
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.33 V ~ 1.47 V
振蕩器型: 外部
工作溫度: -20°C ~ 70°C
封裝/外殼: 400-LFBGA
包裝: 帶卷 (TR)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
97
Ground = 0.0 V; load capacitance = 40 pF; MediaLB speed = 1024 Fs; Fs = 48 kHz; all timing parameters
specified from the valid voltage threshold as listed below unless otherwise noted.
MLB fall time
tmckf
——
3
ns
VIH TO VIL
MLBCLK cycle time
tmckc
81
40
ns
256
× Fs
512
× Fs
MLBCLK low time
tmckl
31.5
30
37
35.5
ns
256
× Fs
256
× Fs PLL unlocked
14.5
14
17
16.5
ns
512
× Fs
512
× Fs PLL unlocked
MLBCLK high time
tmckh
31.5
30
38
36.5
ns
256
× Fs
256
× Fs PLL unlocked
14.5
14
17
16.5
ns
512
× Fs
512
× Fs PLL unlocked
MLBCLK pulse width variation
tmpwv
——
2
ns pp
Note2
MLBSIG/MLBDAT input valid to
MLBCLK falling
tdsmcf
1—
ns
MLBSIG/MLBDAT input hold
from MLBCLK low
tdhmcf
0—
ns
MLBSIG/MLBDAT output high
impedance from MLBCLK low
tmcfdz
0—
tmckl
ns
Bus Hold Time
tmdzh
4—
ns
Note3
1 The MLB controller can shut off MLBCLK to place MediaLB in a low-power state.
2 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (pp)
3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
Table 63. MLB Device 1024Fs Timing Parameters
Parameter
Symbol
Min
Typ
Max
Units
Comment
MLBCLK Operating
Frequency1
fmck
45.056
49.152
49.2544
51.200
MHz
Min: 1024
× Fs at 44.0 kHz
Typ: 1024
× Fs at 48.0 kHz
Max: 1024
× Fs at 48.1 kHz
Max: 1024
× Fs PLL unlocked
MLBCLK rise time
tmckr
——
1
ns
VIL TO VIH
MLB fall time
tmckf
——
1
ns
VIH TO VIL
MLBCLK cycle time
tmckc
20.3
ns
MLBCLK low time
tmckl
6.5
6.1
7.7
7.3
ns
PLL unlocked
Table 62. MLB 256/512 Fs Timing Parameters (continued)
Parameter
Symbol
Min
Typ
Max
Units
Comment
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