參數(shù)資料
型號： MCIMX31CVMN4C
廠商： Freescale Semiconductor
文件頁數(shù)： 16/108頁
文件大?。?/td> 0K
描述： IC MPU MAP I.MX31 473-MAPBGA
標(biāo)準(zhǔn)包裝： 84
系列： i.MX31
核心處理器： ARM11
芯體尺寸： 32-位
速度： 400MHz
連通性： 1 線，ATA，EBI/EMI，F(xiàn)IR，I²C，MMC/SD，PCMCIA，SIM，SPI，SSI，UART/USART，USB，USB OTG
外圍設(shè)備： DMA，LCD，POR，PWM，WDT
程序存儲器類型： ROMless
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 1.22 V ~ 3.3 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 473-LFBGA
包裝： 托盤
Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor
15
4.2
Supply Power-Up/Power-Down Requirements and Restrictions
Any MCIMX31C board design must comply with the power-up and power-down sequence guidelines as
described in this section to guarantee reliable operation of the device. Any deviation from these sequences
may result in any or all of the following situations:
Cause excessive current during power-up phase
Prevent the device from booting
Cause irreversible damage to the MCIMX31C (worst-case scenario)
4.2.1
Powering Up
The Power On Reset (POR) pin must be kept asserted (low) throughout the power-up sequence. Power-up
logic must guarantee that all power sources reach their target values prior to the release (de-assertion) of
POR. Figure 2 and Figure 3 show two options of the power-up sequence.
NOTE
Stages need to be performed in the order shown; however, within each stage,
supplies can be powered up in any order. For example, supplies IOQVDD, NVCC1,
and NVCC3 through NVCC10 do not need to be powered up in the order shown.
CAUTION
NVCC6 and NVCC9 must be at the same voltage potential. These supplies
are connected together on-chip to optimize ESD damage immunity.
Figure 2. Option 1 Power-Up Sequence for Silicon Revision 2.0 and 2.0.1
Release POR
QVCC, QVCC1, QVCC4
IOQVDD, NVCC1, NVCC3–10
NVCC2, NVCC21, NVCC22
Hold POR Asserted
Notes:
1
The board design must guarantee that supplies reach 90% level before
transition to the next state, using Power Management IC or other
means.
2
The NVCC1 supply must not precede IOQVDD by more than 0.2 V until
IOQVDD has reached 1.5 V. If IOQVDD is powered up first, there are
no restrictions.
3
The parallel paths in the flow indicate that supply group NVCC2,
NVCC21, and NVCC22, and supply group FVCC, MVCC, SVCC, and
UVCC ramp-ups are independent.
4
FUSE_VDD should not be driven on power-up for Silicon Revision 2.0
and 2.0.1. This supply is dedicated for fuse burning (programming),
and should not be driven upon boot-up.
5
Raising IOQVDD before NVCC21 produces a slight increase in current
drain on IOQVDD of approximately 3–5 mA. The current increase will
not damage the IC. Refer to Errata ID TLSbo91750 for details.
FVCC, MVCC, SVCC, UVCC
4
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MCIMX31DVKN5D 功能描述:處理器 - 專門應(yīng)用 2.0.1 CONSUMER FULL RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
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