- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69032 > MCIMX27VOP4 (FREESCALE SEMICONDUCTOR INC) 32-BIT, 400 MHz, MICROPROCESSOR, PBGA404 PDF資料下載
參數(shù)資料
| 型號(hào)： | MCIMX27VOP4 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA404 |
| 封裝： | 17 X 17 MM, 0.65 MM PITCH, LEAD FEE, MAPBGA-404 |
| 文件頁(yè)數(shù)： | 46/118頁(yè) |
| 文件大小： | 1159K |
| 代理商： | MCIMX27VOP4 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)當(dāng)前第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)
Signal Descriptions
i.MX27 Data Sheet, Advance Information, Rev. 0.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
33
SSI2_CLK
Serial clock signal that is output in master or input in slave, multiplexed with GPT4_TIN. PC27
SSI2_TXD
Transmit serial data signal, multiplexed with GPT4_TOUT; PC26
SSI2_RXD
Receive serial data, multiplexed with GPT5_TIN; PC25
SSI2_FS
Frame Sync signal which is output in master and input in slave, multiplexed with GPT5_TOUT:
PC24
SSI3_CLK
Serial clock signal which is output in master or input in slave. This signal is multiplexed with
SLCDC2_CLK; through GPIO multiplexed with PC_WAIT_B; PC31.
SSI3_TXD
Transmit serial data signal which is multiplexed with SLCDC2_CS, through GPIO multiplexed
with PC_READY; PC30
SSI3_RXD
Receive serial data which is multiplexed with SLCDC2_RS; through GPIO multiplexed with
PC_VS1; PC29
SSI3_FS
Frame Sync signal which is output in master and input in slave. This signal is multiplexed with
SLCDC2_D0; through GPIO multiplexed with PC_VS1; PC28.
SSI4_CLK
Serial clock signal which is output in master or input in slave; through GPIO multiplexed with
PC_BVD1; PC19
SSI4_TXD
Transmit serial data; through GPIO multiplexed with PC_BVD2; PC18
SSI4_RXD
Receive serial data; through GPIO multiplexed with IOIS16; PC17
SSI4_FS
Frame Sync signal which is output in master and input in slave; PC16
General Purpose Timers (X6)
TIN
Timer Input Capture or Timer Input Clock—The signal on this input is applied to GPT 1–3
simultaneously. This signal is muxed with the Walk-up Guard Mode WKGD signal in the PLL,
Clock, and Reset Controller module, and is also multiplexed with GPT6_TOUT; PC15.
TOUT1
Timer Output signal from General Purpose Timer1 (GPT1). This signal is multiplexed with
SSI1_MCLK and SSI2_MCLK signal of SSI1 and SSI2. The pin name of this signal is simply
TOUT, and is also multiplexed with GPT6_TIN; PC14.
Note: TOUT2, TOUT3 are multiplexed with PWMO pad; GPT4 and GPT5 signals are multiplexed with SSI2 pads.
USB2.0
USBOTG_DIR/TXDM
USB OTG direction/Transmit Data Minus signal, multiplexed with KP_ROW7A; PE2
USBOTG_STP/TXDM
USB OTG Stop signal/Transmit Data Minus signal, multiplexed with KP_ROW6A; PE1
USBOTG_NXT/TXDM
USB OTG NEXT/Transmit Data Minus signal, multiplexed with KP_COL6A; PE0
USBOTG_CLK/TXDM
USB OTG Clock/Transmit Data Minus signal, PE24
USBOTG_DATA7/SUSPEND
USB OTG Data7/Suspend signal, PE25
USBH2_STP/TXDM
USB Host2 Stop signal/Transmit Data Minus signal, PA4
USBH2_NXT/TXDM
USB Host2 NEXT/Transmit Data Minus signal, PA3
USBH2_DATA7/SUSPEND
USB Host2 Data7/Suspend signal, PA2
USBH2_DIR/TXDM
USB Host2 Direction/Transmit Data Minus signal, PA1
Table 3. i.MX27 Signal Descriptions (continued)
Pad Name
Function/Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCIMX31DVKN5D | 32-BIT, 532 MHz, MICROPROCESSOR, PBGA457 |
| MCIMX31DVMN5D | 32-BIT, 532 MHz, MICROPROCESSOR, PBGA473 |
| MCIMX31LDVKN5D | 32-BIT, 532 MHz, MICROPROCESSOR, PBGA457 |
| MCIMX31LCJKN5D | 32-BIT, 532 MHz, MICROPROCESSOR, PBGA457 |
| MCIMX512DVK8C | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA625 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCIMX27VOP4A | 功能描述:處理器 - 專門應(yīng)用 I.MX27 REV 2.1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX27VOP4AR2 | 功能描述:處理器 - 專門應(yīng)用 I.MX27 REV 2.1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX27VOP4R2 | 制造商:Freescale Semiconductor 功能描述:MULTIMEDIA PROCESSOR 404-PIN MA-BGA T/R - Tape and Reel |
| MCIMX27WPDK | 功能描述:開發(fā)板和工具包 - ARM MCIMX27 PDK For WINCE RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評(píng)估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
| MCIMX280CVM4B | 功能描述:處理器 - 專門應(yīng)用 Catskills Rev1.2 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。