參數(shù)資料
型號(hào)： MCIMX27VOP4
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA404
封裝： 17 X 17 MM, 0.65 MM PITCH, LEAD FEE, MAPBGA-404
文件頁數(shù)： 102/118頁
文件大?。?/td> 1159K
代理商： MCIMX27VOP4
i.MX27 Data Sheet, Advance Information, Rev. 0.1
84
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Signal Descriptions
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0)
and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or
the frame sync STFS/SRFS shown in the tables and in the figures.
All timings are on AUDMUX pads when SSI is being used for data transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx
Data (for example, during AC97 mode of operation).
3.5.17.2
SSI Receiver Timing with Internal Clock
Figure 46 and Figure 47 show the SSI receiver timing with internal clock, and Table 46 lists the timing
parameters.
Figure 46. SSI Receiver with Internal Clock Timing Diagram
Synchronous Internal Clock Operation
SS42
SRXD setup before (Tx) CK falling
10.0
—
ns
SS43
SRXD hold after (Tx) CK falling
0
—
ns
SS52
Loading
25
pF
Table 45. SSI Transmitter with Internal Clock Timing Parameters (continued)
ID
Parameter
Min
Max
Unit
SS50
SS48
AD1_TXC
AD1_TXFS (bl)
AD1_TXFS (wl)
AD1_RXD
AD1_RXC
SS1
SS4
SS2
SS51
SS20
SS21
SS49
SS7
SS9
SS11
SS13
SS47
(Output)
(Input)
(Output)
SS3
SS5
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MCIMX280CVM4B 功能描述:處理器 - 專門應(yīng)用 Catskills Rev1.2 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
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