參數(shù)資料
型號(hào): MCIMX27VOP4
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA404
封裝: 17 X 17 MM, 0.65 MM PITCH, LEAD FEE, MAPBGA-404
文件頁數(shù): 44/118頁
文件大小: 1159K
代理商: MCIMX27VOP4
Signal Descriptions
i.MX27 Data Sheet, Advance Information, Rev. 0.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
31
SD3_CMD
SD Command bidirectional signal. This signal is multiplexed with ETMTRACEPKT15 and also
through GPIO PD1 multiplexed with FEC_TXD1.
SD3_CLK
SD Output Clock signal. This signal is through GPIO PD0 multiplexed with FEC_TXD0.
Note: SD3_DATA is multiplexed with ATA_DATA3–0.
UARTs (X6)
UART1_RTS
Request to Send input signal; PE15
UART1_CTS
Clear to Send output signal; PE14
UART1_RXD
Receive Data input signal; PE13
UART1_TXD
Transmit Data output signal, PE12
UART2_RXD
Receive Data input signal. This signal is multiplexed with KP_ROW6 signal from KPP; PE7.
UART2_TXD
Transmit Data output signal. This signal is multiplexed with KP_COL6 signal from KPP; PE6.
UART2_RTS
Request to Send input signal. This signal is multiplexed with KP_ROW7 signal from KPP; PE4.
UART2_CTS
Clear to Send output signal. This signal is multiplexed with KP_COL7 signal from KPP; PE3.
UART3_RTS
Request to Send input signal, PE11
UART3_CTS
Clear to Send output signal; PE10
UART3_RXD
Receive Data input signal; PE9
UART3_TXD
Transmit Data output signal; PE8
Note: UART 4, 5, and 6 are multiplexed with COMS Sensor Interface signals.
Keypad
KP_COL[5:0]
Keypad Column selection signals. KP_COL[7:6] are multiplexed with UART2_CTS and
UART2_TXD respectively. Alternatively, KP_COL6 is also available on the internal factory test
signal TEST_WB2. The Function Multiplexing Control Register in the System Control chapter
must be used in conjunction with programming the GPIO multiplexing (to select the alternate
signal multiplexing) to choose which signal KP_COL6 is available.
KP_ROW[5:0]
Keypad Row selection signals. KP_ROW[7:6] are multiplexed with UART2_RTS and
UART2_RXD signals respectively. The Function Multiplexing Control Register in the System
Control chapter must be used in conjunction with programming the GPIO multiplexing (to select
the alternate signal multiplexing) to choose which signals KP_ROW6 and KP_ROW7 are
available.
Note: KP_COL[7:6] and KP_ROW[7:6] are multiplexed with UART2 signals as show above, also see UARTs table.
PWM
PWMO
PWM Output. This signal is multiplexed with PC_SPKOUT of PCMCIA, as well as TOUT2 and
TOUT3 of the General Purpose Timer module; PE5.
CSPI (X3)
CSPI1_MOSI
Master Out/Slave In signal, PD31
CSPI1_MISO
Master In/Slave Out signal, PD30
Table 3. i.MX27 Signal Descriptions (continued)
Pad Name
Function/Notes
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