i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
102
Freescale Semiconductor
Figure 75. TRST Timing Diagram
Table 78. SJC Timing Parameters
ID
Parameter
All Frequencies
Unit
Min.
Max.
SJ1
TCK cycle time
1001
1 In cases where SDMA TAP is put in the chain, the maximum TCK frequency is limited by the maximum ratio of 1:8 of SDMA
core frequency to TCK. This implies a maximum frequency of 8.25 MHz (or 121.2 ns) for a 66 MHz IPG clock.
—ns
SJ2
TCK clock pulse width measured at VM
2
2 V
M – mid point voltage
40
—
ns
SJ3
TCK rise and fall times
—
3
ns
SJ4
Boundary scan input data set-up time
10
—
ns
SJ5
Boundary scan input data hold time
50
—
ns
SJ6
TCK low to output data valid
—
50
ns
SJ7
TCK low to output high impedance
—
50
ns
SJ8
TMS, TDI data set-up time
10
—
ns
SJ9
TMS, TDI data hold time
50
—
ns
SJ10
TCK low to TDO data valid
—
44
ns
SJ11
TCK low to TDO high impedance
—
44
ns
SJ12
TRST assert time
100
—
ns
SJ13
TRST set-up time to TCK low
40
—
ns
TCK
(Input)
TRST
(Input)
SJ13
SJ12
