參數(shù)資料
型號： MCIMX258CVM4
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA400
封裝： 17 X 17 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-400
文件頁數(shù)： 138/154頁
文件大?。?/td> 1498K
代理商： MCIMX258CVM4
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
84
Freescale Semiconductor
3.7.8
Enhanced Secured Digital Host Controller (eSDHCv2) Timing
Figure 54 shows eSDHCv2 timing, and Table 61 describes the timing parameters (SD1–SD8) used in the
figure. The following definitions apply to values and signals described in Table 61:
LS: low-speed mode. Low-speed card can tolerate clocks up to 400 kHz
FS: full-speed mode. Full-speed MMC card’s clock can reach 20 MHz; full speed SD/SDIO card
clock can reach 25 MHz
HS: high-speed mode. High-speed MMC card’s clock can reach 52 MHz; SD/SDIO card clock can
reach 50 MHz
86
SCKT rising edge to data out valid
—
18.0
13.0
x ck
i ck
ns
87
SCKT rising edge to data out high
impedance6
——
—
21.0
16.0
x ck
i ck
ns
88
SCKT rising edge to transmitter #0 drive
enable negation6
——
—
14.0
9.0
x ck
i ck
ns
89
FST input (bl, wr) setup time before SCKT
falling edge5
——
2.0
18.0
—
x ck
i ck
ns
90
FST input (wl) setup time before SCKT falling
edge
——
2.0
18.0
—
x ck
i ck
ns
91
FST input hold time after SCKT falling edge
—
4.0
5.0
—
x ck
i ck
ns
92
FST input (wl) to data out enable from high
impedance
——
—
21.0
—
ns
93
FST input (wl) to transmitter #0 drive enable
assertion
——
—
14.0
—
ns
94
Flag output valid after SCKT rising edge
—
14.0
9.0
x ck
i ck
ns
95
HCKR/HCKT clock cycle
—
2 x TC
15
—
ns
96
HCKT input rising edge to SCKT output
—
18.0
—
ns
97
HCKR input rising edge to SCKR output
—
18.0
—
ns
1 V
CORE_VDD = 1.00 ± 0.10 V; TJ = –40 °C to 125 °C, CL = 50 pF
2 In the “Characteristics” column, bl = bit length, wl = word length, wr = word length relative
3 In the “Expression” column, T
C = 7.5 ns.
4 For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
5 The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but spreads starting from one serial clock before the first bit clock (same as the bit length frame sync signal),
until the second-to-last bit-clock of the first word in the frame.
6 Periodically sampled and not 100% tested.
Table 60. ESAI General Timing Requirements (continued)
No.
Characteristics1 2
Symbol
Expression3
Min.
Max.
Condition
Unit
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相關代理商/技術參數(shù)
參數(shù)描述
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