MCF532x ColdFire Microprocessor Data Sheet, Rev. 5 Electrical Characteristics Fr" />
參數(shù)資料
型號(hào)： MCF5329CVM240J
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 19/50頁(yè)
文件大?。?/td> 0K
描述： IC MPU RISC 240MHZ 256MAPBGA
標(biāo)準(zhǔn)包裝： 90
系列： MCF532x
核心處理器： Coldfire V3
芯體尺寸： 32-位
速度： 240MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，I²C，SPI，SSI，UART/USART，USB，USB OTG
外圍設(shè)備： DMA，LCD，PWM，WDT
輸入/輸出數(shù)： 94
程序存儲(chǔ)器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.4 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 256-LBGA
包裝： 托盤
MCF532x ColdFire Microprocessor Data Sheet, Rev. 5
Electrical Characteristics
Freescale Semiconductor
26
DD8
Data and Data Mask Output Hold (DQS-->DQ) Relative to
DQS (DDR Write Mode)6
tDQDMI
1.0
—
ns
DD9
Input Data Skew Relative to DQS (Input Setup)7
tDVDQ
—1
ns
DD10
Input Data Hold Relative to DQS8
tDIDQ
0.25
× SD_CLK
+0.5ns
—ns
DD11 DQS falling edge from SDCLK rising (output hold time)
tDQLSDCH
0.5
—
ns
DD12 DQS input read preamble width
tDQRPRE
0.9
1.1
SD_CLK
DD13 DQS input read postamble width
tDQRPST
0.4
0.6
SD_CLK
DD14 DQS output write preamble width
tDQWPRE
0.25
SD_CLK
DD15 DQS output write postamble width
tDQWPST
0.4
0.6
SD_CLK
1 SD_CLK is one SDRAM clock in (ns).
2 Pulse width high plus pulse width low cannot exceed min and max clock period.
3 Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature,
and voltage variations.
4 This specification relates to the required input setup time of today’s DDR memories. The processor’s output setup should be
larger than the input setup of the DDR memories. If it is not larger, the input setup on the memory is in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].
5 The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are
valid for each subsequent DQS edge.
6 This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative
MEM_DQS[0].
7 Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other
factors).
8 Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line
becomes invalid.
Table 11. DDR Timing Specifications (continued)
Num
Characteristic
Symbol
Min
Max
Unit
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MCF5329DS 制造商:ANALOGICTECH 制造商全稱:Advanced Analogic Technologies 功能描述:MCF5329 ColdFire Microprocessor Data Sheet
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