MCF532x ColdFire Microprocessor Data Sheet, Rev. 5 Fr" />
參數(shù)資料
型號: MCF5329CVM240J
廠商: Freescale Semiconductor
文件頁數(shù): 14/50頁
文件大?。?/td> 0K
描述: IC MPU RISC 240MHZ 256MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: MCF532x
核心處理器: Coldfire V3
芯體尺寸: 32-位
速度: 240MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,LCD,PWM,WDT
輸入/輸出數(shù): 94
程序存儲器類型: ROMless
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.4 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
包裝: 托盤
Electrical Characteristics
MCF532x ColdFire Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
21
Figure 6. General Input Timing Requirements
5.6.1
FlexBus
A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up
to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such as external
boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For
asynchronous devices a simple chip-select based interface can be used. The FlexBus interface has six general purpose
chip-selects (FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory interfaces.
Chip-select, FB_CS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or
longword (32 bits) wide. Control signal timing is compatible with common ROM/flash memories.
5.6.1.1
FlexBus AC Timing Characteristics
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the system clock.
Table 9. FlexBus AC Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
Frequency of Operation
fsys/3
—80
Mhz
FB1
Clock Period (FB_CLK)
tFBCK (tcyc)
12.5
ns
FB2
Address, Data, and Control Output Valid (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)1
tFBCHDCV
—7.0
ns
FB3
Address, Data, and Control Output Hold (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)1, 2
tFBCHDCI
1—
ns
Invalid
FB_CLK (80MHz)
TSETUP
THOLD
Input Setup And Hold
1.5V
trise
Vh = VIH
Vl = VIL
1.5V
1.5V Valid
tfall
Vh = VIH
Vl = VIL
Input Rise Time
Input Fall Time
* The timings are also valid for inputs sampled on the negative clock edge.
Inputs
FB_CLK
B4
B5
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