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MCF5307 User’s Manual
Real-Time Trace Support
5.3.1 Begin Execution of Taken Branch (PST = 0x5)
PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may
be displayed on DDATA depending on the CSR settings. CSR also controls the number of
address bytes displayed, which is indicated by the PST marker value immediately
preceding the DDATA nibble that begins the data output.
Table 5-2. Processor Status Encoding
PST[3:0]
Denition
Hex
Binary
0x0
0000
Continue execution. Many instructions execute in one processor cycle. If an instruction requires more
clock cycles, subsequent clock cycles are indicated by driving PST outputs with this encoding.
0x1
0001
Begin execution of one instruction. For most instructions, this encoding signals the rst clock cycle of
an instruction’s execution. Certain change-of-ow opcodes, plus the PULSE and WDDATA instructions,
generate different encodings.
0x2
0010
Reserved
0x3
0011
Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor to
enter user mode.
0x4
0100
Begin execution of PULSE and WDDATA instructions. PULSE denes logic analyzer triggers for debug
and/or performance analysis. WDDATA lets the core write any operand (byte, word, or longword)
directly to the DDATA port, independent of debug module conguration. When WDDATA is executed, a
value of 0x4 is signaled on the PST port, followed by the appropriate marker, and then the data transfer
on the DDATA port. Transfer length depends on the WDDATA operand size.
0x5
0101
Begin execution of taken branch. For some opcodes, a branch target address may be displayed on
DDATA depending on the CSR settings. CSR also controls the number of address bytes displayed,
indicated by the PST marker value preceding the DDATA nibble that begins the data output. See
0x6
0110
Reserved
0x7
0111
Begin execution of return from exception (RTE) instruction.
0x8–
0xB
1000–
1011
Indicates the number of bytes to be displayed on the DDATA port on subsequent clock cycles. The
value is driven onto the PST port one clock PSTCLK cycle before the data is displayed on DDATA.
0x8 Begin 1-byte transfer on DDATA.
0x9 Begin 2-byte transfer on DDATA.
0xA Begin 3-byte transfer on DDATA.
0xB Begin 4-byte transfer on DDATA.
0xC
1100
Exception processing. Exceptions that enter emulation mode (debug interrupt or optionally trace)
generate a different encoding, as described below. Because the 0xC encoding denes a multiple-cycle
mode, PST outputs are driven with 0xC until exception processing completes.
0xD
1101
Entry into emulator mode. Displayed during emulation mode (debug interrupt or optionally trace).
Because this encoding denes a multiple-cycle mode, PSToutputs are driven with 0xD until exception
processing completes.
0xE
1110
Processor is stopped. Appears in multiple-cycle format when the MCF5307 executes a STOP
instruction. The ColdFire processor remains stopped until an interrupt occurs, thus PST outputs
display 0xE until the stopped mode is exited
.
0xF
1111
Processor is halted. Because this encoding denes a multiple-cycle mode, the PST outputs display
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Freescale Semiconductor, Inc.
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