Chapter 4. Local Memory
4-13
Cache Operation
Normally, cache-inhibited reads bypass the cache and are performed on the external bus.
The exception to this normal operation occurs when all of the following conditions are true
during a cache-inhibited read:
The cache-inhibited ll buffer bit, CACR[DNFB], is set.
The access is an instruction read.
The access is normal (that is, transfer type (TT) equals 0).
In this case, an entire line is fetched and stored in the ll buffer. It remains valid there, and
the cache can service additional read accesses from this buffer until either another ll or a
cache-invalidate-all operation occurs.
Valid cache entries that match during cache-inhibited address accesses are neither pushed
nor invalidated. Such a scenario suggests that the associated cache mode for this address
space was changed. To avoid this, it is generally recommended to use the CPUSHL
instruction to push or invalidate the cache entry or set CACR[CINVA] to invalidate the
cache before switching cache modes.
4.9.1 Caching Modes
For every memory reference generated by the processor or debug module, a set of effective
attributes is determined based on the address and the ACRs. Caching modes determine how
the cache handles an access. An
access can be cacheable in either write-through or
copyback mode; it can be cache-inhibited in precise or imprecise modes. For normal
accesses, the ACRn[CM] bit corresponding to the address of the access species the
caching modes. If an address does not match an ACR, the default caching mode is dened
by CACR[DCM]. The specic algorithm is as follows:
if (address == ACR0-address including mask)
effective attributes = ACR0 attributes
else if (address == ACR1-address including mask)
effective attributes = ACR1 attributes
else effective attributes = CACR default attributes
Addresses matching an ACR can also be write-protected using ACR[W]. Addresses that do
not match either ACR can be write-protected using CACR[DW].
Reset disables the cache and clears all CACR bits. As shown in
Figure 4-4, reset does not
automatically invalidate cache entries; they must be invalidated through software.
The ACRs allow the defaults selected in the CACR to be overridden. In addition, some
instructions (for example, CPUSHL) and processor core operations perform accesses that
have an implicit caching mode associated with them. The following sections discuss the
different caching accesses and their associated cache modes.
4.9.1.1 Cacheable Accesses
If ACRn[CM] or the default eld of the CACR indicates write-through or copyback, the
access is cacheable. A read access to a write-through or copyback region is read from the
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