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Electrical Characteristics
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
23-26
Freescale Semiconductor
Figure 23-19. GCI Slave Mode Timing
Table 23-20. GCI Master Mode Timing, PLIC PORTs 1, 2, 3
Name
Characteristic
Min
Max
Unit
Name
P50 1
1 For most telecommunications applications the period of DFSC[1:3] should be set to 125 S. Refer to clock generator planning
in PLIC chapter.
Delay from rising edge of GDCL1_OUT to rising edge of DFSC[1:3]
—
20
nS
Delay from rising edge of GDCL1_OUT to falling edge of DFSC[1:3]
—
20
nS
P52 2,3
2 GDCL1_OUT must be less than 1/20th of the CPU operating frequency to ensure minimum jitter to CODECs connected to
Ports 1, 2, 3.
3 Same as DCL0 and FSC0 if internal clock generator configured for pass-through mode.
GDCL1_OUT clock period
20T
—
nS
4 Based on generated GDCL1_OUT less than 1/20 of CPU clock frequency.
GDCL1_OUT pulse-width low
45
50
55
% of period
P54
2,4 GDCL1_OUT pulse-width high
45
50
55
% of period
P57
Delay from rising edge of GDCL1_OUT to Low-Z and valid data on DOUT[1,3]
—
30
nS
P58
Delay from rising edge of GDCL1_OUT to data valid on DOUT[1,3]
—
30
nS
P59
Delay from rising edge of GDCL1_OUT to High-Z on DOUT[1,3]
—
30
nS
P60
Data valid on DIN[1:3] before rising edge of GDCL1_OUT (setup time)
25
—
nS
P61
Data valid on DIN[1:3] after rising edge of GDCL1_OUT (hold time)
25
—
nS
DOUT[0,1,3]
FSC[0,1]
DCL[0:1]
P35
P34
P40
P39
P38
P30
P32
P31
P42
P41
P33
DIN[0,1,3]
DFSC[2,3]