Signal Descriptions
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
19-7
MTMOD
—
0 selects JTAG mode, 1
selects BDM mode
B3
I
OE/RD
—
Output enable/Read
P13
O
4
30
Port A Cntl
PA0
USB_TP
—
Port A bit 0/
USB Tx positive
D2
I/O
2
30
Port A Cntl
PA1
USB_RP
—
Port A bit 1/
USB Rx positive
D1
I/O
2
30
Port A Cntl
PA10
DREQ0
—
Port A bit 10/IDL DREQ0
K5
I/O
2
30
Port A Cntl
PA11
—
QSPI_CS1
—
Port A bit 11/QSPI chip
select 1
L1
I/O
2
30
Port A Cntl
PA12
DFSC2
—
Port A bit 12/Delayed
frame sync 2
L2
I/O
2
30
Port A Cntl
PA13
DFSC3
—
Port A bit 13/Delayed
frame sync 3
L3
I/O
2
30
Port A Cntl
PA14
DREQ1
—
Port A bit 14/PLIC port 1
IDL D-channel request
M2
I/O
4
30
Port A Cntl
PA15_INT6
DGNT1_INT6
—
Port A bit 15/PLIC port 1
D-channel grant/Interrupt
6 input
M3
I/O
2
30
Port A Cntl
PA2
USB_RN
—
Port A bit 2/
USB Rx negative
E5
I/O
2
30
Port A Cntl
PA3
USB_TN
—
Port A bit 3/
USB Tx negative
E4
I/O
2
30
Port A Cntl
PA4
USB_
Susp
—
Port A bit 4/
Suspend USB driver
E3
I/O
2
30
Port A Cntl
PA5
USB_TxEN
—
Port A bit 5/USB
transmitter enable
E2
I/O
2
30
Port A Cntl
PA6
USB_RxD
—
Port A bit 6/USB receive
data output
E1
I/O
2
30
Port A Cntl
PA7
QSPI_CS3
DOUT3
—
PA7/QSPI chip select
4/PLIC port 3 data output
P1
I/O
2
30
Port A Cntl
PA8
FSC0/
FSR0
—
Port A bit 8/IDL FSR0 &
GCI FSC0
J2
I/O
2
30
Port A Cntl
PA9
DGNT0
—
Port A bit 9//IDL DGNT0
J3
I/O
2
30
Port B Cntl
PB0
URT0_TxD
—
Port B bit 0/UART0 Tx
data
H4
I/O
4
30
Port B Cntl
PB1
URT0_RxD
—
Port B bit 1/UART0 Rx
data
H1
I/O
2
30
Table 19-1. Signal Descriptions Sorted by Function (Sheet 5 of 8)
Configured
by
(see notes)1
Pin Functions
Description
Map
BGA
Pin
I/O
Drive
(mA)
Cpf
0 (Reset)
1
2
3