參數(shù)資料
型號(hào): MCF5270
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 32-bit Embedded Controller Division
中文描述: 32位嵌入式控制器部
文件頁(yè)數(shù): 9/56頁(yè)
文件大小: 1096K
代理商: MCF5270
Features
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2
Freescale Semiconductor
9
system stack, or for storing FEC data buffers. Because the SRAM module is physically connected to the
processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing
commands from the debug module.
The SRAM module is also accessible by the DMA and FEC non-core bus masters. The dual-ported nature
of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the
processor and a DMA device operate in alternate regions of the SRAM to maximize system performance.
As an example, system performance can be increased significantly if Ethernet packets are moved from the
FEC into the SRAM (rather than external memory) prior to any processing.
3.6
Fast Ethernet Controller (FEC)
The MCF5271’s integrated Fast Ethernet Controller (FEC) performs the full set of IEEE 802.3/Ethernet
CSMA/CD media access control and channel interface functions. The FEC supports connection and
functionality for the 10/100 Mbps 802.3 media independent interface (MII). It requires an external
transceiver (PHY) to complete the interface to the media.
3.7
UARTs
The MCF5271 contains three full-duplex UARTs that function independently. The three UARTs can be
clocked by the system bus clock, eliminating the need for an externally supplied clock. They can use DMA
requests on transmit-ready and receive-ready as well as interrupt requests for servicing. Flow control is
only available on two of the UARTs.
3.8
I
2
C Bus
The I
2
C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data
exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring
occasional communications over a short distance between many devices.
3.9
QSPI
The queued serial peripheral interface module provides a high-speed synchronous serial peripheral
interface with queued transfer capability. It allows up to 16 transfers to be queued at once, eliminating CPU
intervention between transfers.
3.10 Cryptography
The superset device, MCF5271, incorporates small, fast, dedicated hardware accelerators for random
number generation, message digest and hashing, and the DES, 3DES, and AES block cipher functions
allowing for the implementation of common Internet security protocol cryptography operations with
performance well in excess of software-only algorithms.
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MCF5270CVM150J 功能描述:32位微控制器 - MCU V2CORE RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT
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