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參數(shù)資料
| 型號： | MCF5270 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | 32-bit Embedded Controller Division |
| 中文描述： | 32位嵌入式控制器部 |
| 文件頁數(shù)： | 33/56頁 |
| 文件大?。?/td> | 1096K |
| 代理商： | MCF5270 |
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Preliminary Electrical Characteristics
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2
Freescale Semiconductor
33
8.2
Thermal Characteristics
Table 27
lists thermal resistance values
2
This device contains circuitry protecting against damage due to high static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid application of
any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.,
either V
SS
or OV
DD
).
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages,
then use the larger of the two values.
All functional non-supply pins are internally clamped to V
SS
and OV
DD
.
Power supply must maintain regulation within operating OV
DD
range during instantaneous
and operating maximum current conditions. If positive injection current (V
in
> OV
DD
) is greater
than I
DD
, the injection current may flow out of OV
DD
and could result in external power supply
going out of regulation. Insure external OV
DD
load will shunt current greater than maximum
injection current. This will be the greatest risk when the processor is not consuming power
(ex; no clock).Power supply must maintain regulation within operating OV
DD
range during
instantaneous and operating maximum current conditions.
3
4
5
Table 27. Thermal Characteristics
Characteristic
Symbol
196
MAPBGA
160QFP
Unit
Junction to ambient, natural convection
Four layer board (2s2p)
θ
JMA
θ
JMA
θ
JB
θ
JC
Ψ
jt
32
1,2
NOTES:
1
θ
JMA
and
Ψ
jt
parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.
Motorola recommends the use of
θ
JmA
and power dissipation specifications in the system design to prevent
device junction temperatures from exceeding the rated specification. System designers should be aware that
device junction temperatures can be significantly influenced by board layout and surrounding devices.
Conformance to the device junction temperature specification can be verified by physical measurement in the
customer’s system using the
Ψ
jt
parameter, the device power dissipation, and the method described in
EIA/JESD Standard 51-2.
2
Per JEDEC JESD51-6 with the board horizontal.
3
θ
JMA
and
Ψ
jt
parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.
Motorola recommends the use of
θ
JmA
and power dissipation specifications in the system design to prevent
device junction temperatures from exceeding the rated specification. System designers should be aware that
device junction temperatures can be significantly influenced by board layout and surrounding devices.
Conformance to the device junction temperature specification can be verified by physical measurement in the
customer’s system using the
Ψ
jt
parameter, the device power dissipation, and the method described in
EIA/JESD Standard 51-2.
4
Per JEDEC JESD51-6 with the board horizontal.
5
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8.
Board temperature is measured on the top surface of the board near the package.
6
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8.
Board temperature is measured on the top surface of the board near the package.
40
3,4
°
C / W
Junction to ambient (@200 ft/min)
Four layer board (2s2p)
29
5
,
6
36
5
,
6
°
C / W
Junction to board
20
5
25
6
°
C / W
Junction to case
10
7
10
8
°
C / W
Junction to top of package
2
5
,9
2
5
,10
°
C / W
Maximum operating junction temperature
T
j
104
105
o
C
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