
System Protection And Reset Status
MOTOROLA
System Integration Module
9-15
9.4.3
SOFTWARE INTERRUPTS
The MCF5249 supports four software interrupts. These interrupts are activated by writing a “1” to an
extraInt register bit. When active, the interrupts can generate a normal interrupt exception to the ColdFire
processor. The interrupt exception is only generated if the corresponding level register interrupt mask is
higher than the current processor interrupt mask.
Table 9-24 Extraint Register Descriptions
Note:
Bits 7-4 of the register return on read the value of the software interrupts 0-3. When written zero, the value of the corresponding software
interrupt will not change. When written one, the corresponding software interrupt is set to 1.
Note:
Bits 3-0 of the register return on read the value of software interrupts 0-3. When written zero, the value of the corresponding software
interrupt will not change. When written one, the corresponding software interrupt is set to 0.
9.5
SYSTEM PROTECTION AND RESET STATUS
9.5.1
RESET STATUS REGISTER
The RSR contains a bit for each reset source to the SIM. A bit set to 1 indicates the last type of reset that
occurred. The RSR is updated by the reset control logic on completion of the reset operation. Only one bit
will be set at any given time in the RSR. The register reflects the cause of the most recent reset. If a reset
occurs and the user failed to clear this register, reset control logic will clear all bits and set the appropriate
bit to indicate the current cause of reset. The RSR programming model is illustrated as follows.
The Reset Status Register (RSR) is an 8-bit supervisor read-write register.
10
RCV2FULL
interrupt set if receive buffer reg 2 full
read data
57
11
TX2EMPTY
interrupt set if transmit buffer reg 2 empty
write data
57
EXTRAINT
MBAR2 + 198
BIT FIELD
NAME
ACCESS
DESCRIPTION
INT NO
NOTE
3,7
SOFTINT3
R
read softint3 value
50
1,2
2,6
SOFTINT2
R
read softint2 value
49
1,2
1,5
SOFTINT1
R
read softint1 value
48
1,2
0,4
SOFTINT0
R
read softint0 value
47
1,2
7
SOFTINT3_SET
W
write one to this bit to set softint3
50
1
6
SOFTINT2_SET
W
write one to this bit to set softint2
49
1
5
SOFTINT1_SET
W
write one to this bit to set softint1
48
1
4
SOFTINT0_SET
W
write one to this bit to set softint0
47
1
3
SOFTINT3_CLR
W
write one to this bit to clear softint3
50
2
SOFTINT2_CLR
W
write one to this bit to clear softint2
49
2
1
SOFTINT1_CLR
W
write one to this bit to clear softint1
48
2
0
SOFTINT0_CLR
W
write one to this bit to clear softint0
47
2
Table 9-23 FlashMedia Interrupt Interface (Continued)
FLASHMEDIAINTSTAT
FLASHMEDIAINTEN
FLASHMEDIAINTCLEAR BITS
INT NAME
MEANING
RESET
INTERRUPT
ASSOCIATED
INTERRUPT
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Freescale Semiconductor, Inc.
For More Information On This Product,
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