17-14
MCF5249UM
MOTOROLA
Digital Audio Interface (EBU)
17.3.1.5
IEC958 Exception Definition
There are several IEC958 exceptions defined that will trigger an interrupt. These are:
Control channel change — Set when EBURcvCChannel register is updated. The register is updated
for every new C-Channel received. The exception is reset when EBURcvCChannel register is read.
EBU Illegal Symbol — Set on reception of illegal symbol during IEC958 receive. Reset by writing
register InterruptClear. Refer to the section on interrupts for details. The EBU input is a biphase/mark
modulated signal. The time between any two successive transitions of the EBU signal is always 1, 2
or 3 EBU symbol periods long. The EBU receiver will parse the stream, and split it in so-called
symbols. It recognizes s1, s2 and s3 symbols, depending on the length of the symbols. Not all
sequences of these symbols are allowed. To give an example, a sequence s2-s1-s1-s1-s2 cannot
occur in a error-free EBU signal. If the receiver finds such an illegal sequence, the illegal symbol
interrupt is set. No corrective action is undertaken.
When the interrupt occurs, this means that
(a) The EBU signal is destroyed by noise
(b) The EBU frequency changed.
IEC958 bit error — Set on reception of bit error. (Parity bit does not match). Reset on write to
InterruptClear register. Refer to the section on interrupts for details.
17.3.1.6
EBU Extracted Clock
The clock from the EBU signal is extracted for measurement purposes only. It cannot be used as a clock to
drive other audio interfaces like IIS. The average rate is 128 x the sampling frequency (ex. 128 * 44.1 KHz
for 44.1 KHz input sampling frequency). The internal signal is used in the FreqMeas circuit to generate the
frequency measurement.
17.3.1.7
Reception of User Channel and CD-subcode Over IEC958 Receiver
The IEC958 receiver is capable of extracting the User Channel bits out of the data stream. The extracted
bits are assembled in the 32-bit “UChannelReceive” register, with the first U-Channel bit in the MSB
position (bit 31). The interface can be configured to detect Sync patterns in the U-Channel in the case the
U-Channel contains CD subcode (CD-mode). The Sync Detection can be enabled by setting the
USyncMode bits in the CD-Subcode register
(Table 17-15). Sync recognition is done as follows:
–
Internally, a symbol starting with a “1” is treated as a “data symbol”. Any consecutive 11 zeros
are treated as a “zero symbol”
–
The sync detector will assume User Channel sync whenever:
(a) A sequence of 4 symbols, data-sync-sync-data, is found.
(b) 98 symbols (does not matter data or zero) after the previous “sync symbols”
–
The ChannelLengthError interrupt is set when a new sync is not found at the correct distance
from the previous sync, or if UChannelReceive or QChannelReceive do not contain the correct
number of bits/bytes.
Furthermore, in CD-mode, the Q-channel receiver extracts the Q-channel CD-Subcode from the
U-Channel stream and assembles the bits in the 32-bit “QChannelReceive” with the first bit in the MSB
position.
Associated registers are shown in the following table:
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Freescale Semiconductor, Inc.
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