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TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
MOTOROLA
USERS MANUAL
iii
2.13.2
Debug Data (PP[3:0]/DDATA[3:0])........................................... 2-17
2.13.3
Development Serial Clock (TRST/DSCLK) ..............................2-17
2.13.4
Break Point (TMS/BKPT) .........................................................2-17
2.13.5
Development Serial Input (TDI/DSI) .........................................2-18
2.13.6
Development Serial Output (TDO/DSO) ..................................2-18
2.14
JTAG Signals .....................................................................................2-18
2.14.1
Test Clock (TCK) ......................................................................2-18
2.14.2
Test Reset (TRST/DSCLK) ......................................................2-18
2.14.3
Test Mode Select (TMS/BKPT) ................................................2-19
2.14.4
Test Data Input (TDI/DSI) .........................................................2-19
2.14.5
Test Data Output (TDO/DSO) ..................................................2-19
2.15
Test Signals ........................................................................................2-19
2.15.1
Motorola Test Mode (MTMOD) ................................................2-19
2.15.2
High Impedance (HIZ) ..............................................................2-20
2.16
Signal Summary .................................................................................2-20
Section 3
ColdFire Core
3.1
Processor Pipelines ..............................................................................3-1
3.2
Processor Register Description ............................................................3-2
3.2.1
User Programming Model ..........................................................3-2
3.2.1.1
Data Registers (D0D7) .................................................3-2
3.2.1.2
Address Registers (A0A6) ............................................3-2
3.2.1.3
Stack Pointer (A7) ...........................................................3-2
3.2.1.4
Program Counter (PC).....................................................3-2
3.2.1.5
Condition Code Register (CCR) ......................................3-3
3.2.2
Supervisor Programming Model .................................................3-4
3.2.2.1
Status Register ...............................................................3-4
3.2.2.2
Vector Base Register (VBR) ...........................................3-5
3.3
Exception Processing Overview ...........................................................3-5
3.4
Exception Stack Frame Definition ........................................................3-7
3.5
Processor Exceptions ...........................................................................3-8
3.5.1
Access Error Exception ..............................................................3-8
3.5.2
Address Error Exception ............................................................3-9
3.5.3
Illegal Instruction Exception ........................................................3-9
3.5.4
Privilege Violation .......................................................................3-9
3.5.5
Trace Exception .........................................................................3-9
3.5.6
Debug Interrupt ........................................................................3-10
3.5.7
RTE and Format Error Exceptions ...........................................3-10
3.5.8
TRAP Instruction Exceptions ....................................................3-10
3.5.9
Interrupt Exception ...................................................................3-10
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Freescale Semiconductor, Inc.
For More Information On This Product,
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