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MOTOROLA
MCF5206 USERS MANUAL Rev 1.0
i
TABLE OF CONTENTS
Paragraph
Page
Number
Title
Number
Section 1
Introduction
1.1
Background .......................................................................................... 1-1
1.2
MCF5206 Features .............................................................................. 1-2
1.3
Functional Blocks ................................................................................. 1-4
1.3.1
ColdFire Processor Core............................................................ 1-4
1.3.1.1
Processor States ............................................................1-4
1.3.1.2
Programming Model ....................................................... 1-5
1.3.1.3
Data Format Summary ................................................... 1-8
1.3.1.4
Addressing Capabilities Summary ..................................1-8
1.3.1.5
Notational Conventions................................................... 1-8
1.3.1.6
Instruction Set Overview................................................. 1-8
1.3.2
Instruction Cache ..................................................................... 1-14
1.3.3
Internal SRAM ..........................................................................1-14
1.3.4
DRAM Controller ...................................................................... 1-14
1.3.5
DUART Module ........................................................................ 1-15
1.3.6
Timer Module ........................................................................... 1-15
1.3.7
Motorola Bus (M-Bus) Module.................................................. 1-15
1.3.8
System Interface ...................................................................... 1-15
1.3.8.1
External Bus Interface .................................................. 1-15
1.3.8.2
Chip Selects.................................................................. 1-16
1.3.9
8-Bit Parallel Port (General-Purpose I/O)................................. 1-16
1.3.10
Interrupt Controller ................................................................... 1-16
1.3.11
System Protection .................................................................... 1-16
1.3.12
JTAG ........................................................................................ 1-16
1.3.13
System Debug Interface........................................................... 1-16
1.3.14
Pinout and Package ................................................................. 1-17
Section 2
Signal Description
2.1
Introduction........................................................................................... 2-1
2.2
Address Bus .........................................................................................2-3
2.2.1
Address Bus (A[27:24]/ CS[7:4]/ WE[0:3]) ................................. 2-4
2.2.2
Address Bus (A[23:0]) ................................................................ 2-4
2.2.3
Data Bus (D[31:0])...................................................................... 2-4
2.3
Chip Selects ......................................................................................... 2-4
2.3.1
Chip Selects (A[27:24]/ CS[7:4]/ WE[0:3]).................................. 2-5
Date: 8-31-98
Revision No.: 1.1
Pages affected: See change bars
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Freescale Semiconductor, Inc.
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