參數(shù)資料
型號(hào)： MC9328MXLDVP15
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 150 MHz, RISC PROCESSOR, PBGA225
封裝： 13 X 13 MM, 0.80 MM PITCH, MAPBGA-225
文件頁(yè)數(shù)： 55/89頁(yè)
文件大?。?/td> 1869K
代理商： MC9328MXLDVP15
Specifications
MOTOROLA
MC9328MXL Advance Information
59
3.13 Pulse-Width Modulator
The PWM can be programmed to select one of two clock signals as its source frequency. The selected
clock signal is passed through a divider and a prescaler before being input to the counter. The output is
available at the pulse-width modulator output (PWMO) external pin. Its timing diagram is shown in
Figure 47 and the parameters are listed in Table 21.
Figure 47. PWM Output Timing Diagram
3.14 SDRAM Controller
A write to an address within the memory region initiates the program sequence. The first command issued
to the SyncFlash is Load Command Register. The value in A [7:0] determines which operation the
command performs. For this write setup operation, an address of 0x40 is hardware generated. The bank
and other address lines are driven with the address to be programmed. The next command is Active which
registers the row address and confirms the bank address. The third command supplies the column address,
re-confirms the bank address, and supplies the data to be written. SyncFlash does not support burst writes,
therefore a Burst Terminate command is not required.
A read to the memory region initiates the status read sequence. The first command issued to the SyncFlash
is the Load Command Register with A [7:0] set to 0x70 which corresponds to the Read Status Register
operation. The bank and other address lines are driven to the selected address. The second command is
Table 21. PWM Output Timing Parameter Table
Ref
No.
Parameter
1.8V ± 0.10V
3.0V ± 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
1
System CLK frequency1
1.
CL of PWMO = 30 pF
0870
100
MHz
2a
Clock high time1
3.3
—
5/10
—
ns
2b
Clock low time1
7.5
—
5/10
—
ns
3a
Clock fall time1
—5—
5/10
ns
3b
Clock rise time1
—
6.67
—
5/10
ns
4a
Output delay time1
5.7
—
5
—
ns
4b
Output setup time1
5.7
—
5
—
ns
System Clock
2a
1
PWM Output
3b
2b
3a
4b
4a
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