參數(shù)資料
型號: MC9328MXLDVP15
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 150 MHz, RISC PROCESSOR, PBGA225
封裝: 13 X 13 MM, 0.80 MM PITCH, MAPBGA-225
文件頁數(shù): 13/89頁
文件大小: 1869K
代理商: MC9328MXLDVP15
20
MC9328MXL Advance Information
MOTOROLA
Specifications
3.8.1 DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 HCLK counts have elapsed. Only CS5 group is
designed to support DTACK signal function when using the external DTACK signal for data
acknowledgement.
3.8.2 DTACK Signal Timing
Figure 6 shows the access cycle timing used by chip-select 5. The signal values and units of measure for
this figure are found in Table 12.
Figure 6. DTACK Timing, WSC=111111, DTACK_sel=0
Table 12. Access Cycle Timing Parameters
Ref
No.
Characteristic
1.8V ± 0.10V
3.0V ± 0.30V
Unit
Min
Max
Min
Max
1CS5 asserted to OE asserted
—T—T
ns
2
External DTACK input setup from CS5
asserted
0—0—
ns
3CS5 pulse width
3T
3T
ns
4
External DTACK input hold after CS5 is
negated
0
1.5T
0
1.5T
ns
5OE negated after CS5 is negated
0
4.5
0
4
ns
Note:
1. n is the number of wait states in the current memory access cycle. The max n is 1022.
2. T is the system clock period (system clock is 96 MHz).
3. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
CS5
RW
OE
EXT_DTACK
HCLK
INT_DTACK
1
2
3
4
5
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