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參數(shù)資料
| 型號： | MC92600JUB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA217 |
| 封裝： | 23 X 23 MM, 2.32 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-217 |
| 文件頁數(shù)： | 36/98頁 |
| 文件大小： | 1288K |
| 代理商： | MC92600JUB |
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MOTOROLA
Chapter 3. Receiver
3-13
Device Operations
3.5.4.2
10-Bit Interface Mode
Received data is ten bits of coded data when in TBI mode. The internal 8B/10B decoder is
not used, and it is assumed that decoding is done externally. 10-bit data is made up from the
collection of signals— RECV_x_9, RECV_x_K, and RECV_x_7 through RECV_x_0
making up bits 9 through 0, respectively. 10-bit interface mode is enabled by setting the
TBIE signal high.
The RECV_x_IDLE is asserted when the 10-bit character is the special 8B/10B idle
(K28.5) code. This can be used by system logic for synchronization or data parsing.
RECV_x_IDLE is set low when the data is normal data or a non-idle special code.
The RECV_x_ERR is set low when the receiver is operating normally, and is asserted when
the receiver is in an error state. The state of the RECV_x_IDLE signal is decoded to
determine the error condition. Table 3-6 describes the error codes and their meaning.
The receiver interface is timed to the recovered clock, RECV_x_RCLK, or to the reference
clock, REF_CLK, depending on the state of the RCCE signal.
3.5.4.3
Double Data Rate Mode
Double data rate (DDR) mode, enabled when DDRE is asserted, allows the received data
to be output on the rising and falling edges of a reference or recovered clock. DDR mode
is used to lower reference clock frequency while maintaining throughput, reducing board
design complications. It is important to note that in DDR mode the legal range of reference
clock frequencies is reduced. Table 4-1, "Legal Reference Clock Frequency Ranges” shows
legal reference clock frequencies for all modes of operation.
3.5.4.4
Half-Speed Mode
Half-speed (HS) mode, enabled when HSE is asserted, operates the receiver in its lower
speed range. In HS mode, the link speed is 500 Mbps (625 Mbaud.) The receiver interface
operates at half speed as well, in pace with received data.
3.5.4.5
Repeater Mode
Repeater mode congures the MC92600 into a 4-link receive-transmit repeater. In this
mode, received data is forwarded to the transmitter for re-transmission. Link A’s receiver
forwards to link A’s transmitter, link B’s receiver to link B’s transmitter, and so on. The
receiver’s data outputs and status signals reect the received data and the current status of
the receiver. See Section 2.3.2, “Repeater Mode” for more information on repeater mode.
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| MC92603VF | 功能描述:IC TXRX ETH QUAD GIG 256-MAPBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:25 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應商設備封裝:16-PDIP 包裝:管件 |
| MC92603VM | 功能描述:IC ETH TXRX QUAD GIG 256-MAPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:1,000 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR) |
| MC92604VM | 功能描述:IC ETH TXRX DUAL GIG 196-MAPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:1,000 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR) |
| MC92604ZT | 功能描述:IC TXRX ETH DUAL GIG 196-MAPBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:25 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應商設備封裝:16-PDIP 包裝:管件 |
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