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參數(shù)資料
| 型號： | MC92600JUB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA217 |
| 封裝： | 23 X 23 MM, 2.32 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-217 |
| 文件頁數(shù)： | 32/98頁 |
| 文件大?。?/td> | 1288K |
| 代理商： | MC92600JUB |
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3-10
MC92600 SERDES User’s Manual
MOTOROLA
Device Operations
In an overrun situation, a byte of data needs to be dropped to maintain synchronization
between the clock domains. The receiver interface searches for an idle byte to drop when
overrun is imminent. However, the idle is dropped only if add/delete idle (ADI) mode is
enabled by setting ADIE high. When enabled, idle patterns are dropped to maintain
synchronization. If sufcient idle patterns are not available to drop, receiver overrun may
occur. When overrun occurs, the overrun/underrun error is reported as described in
Section 3.6, “Receiver Interface Error Codes,” for one byte clock period. Overrun error is
also reported if ADI mode is disabled and overrun occurs, even if idles are available to drop.
A sufcient number of idles must be transmitted to guard against overrun. The frequency
of idles can be computed based upon the maximum frequency offset between transmitter
and receiver in the system. The number of bytes (characters) that can be transmitted
between idles is:
(106 / N) - 1 bytes
where:
N is the frequency offset in ppm.
In an underrun situation, a byte of data needs to be added to maintain synchronization
between the clock domains. The receiver interface adds an idle byte when underrun is
imminent. However, the idle is added only if add/delete idle (ADI) mode is enabled by
asserting ADIE. If ADI mode is disabled and underrun occurs, the overrun/underrun error
is reported as described in Section 3.6 for one byte clock period.
Data is timed to the rising edge of the reference clock signal except in double data rate mode
where data is timed to the rising and falling edges of the reference clock.
3.5
Device Operations
The MC92600 receiver is comprised of several devices and operations that are described in
the following sections.
3.5.1
Receiver Input Amplier
The input amplier connects directly to the link input pads RLINK_x_P and RLINK_x_N.
It is a differential amplier with an integrated analog multiplexer for loop-back testing.
Link termination resistors are integrated with the amplier. The termination resistance is
programmable to be 100
differential or 150 differential through the MEDIA signal.
Termination resistance is 100
when MEDIA is low and 150 when MEDIA is high.
The input amplier facilitates a loop-back path for production and in-system testing. When
the MC92600 is in loop-back mode (LBE is high), the input amplier selects the loop-back
differential input signals and ignores the state on the RLINK_x_P and RLINK_x_N signals.
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