Preliminary
MC80F0208/16/24
MAR. 2005 Ver 0.2
29
00F4
Watch dog timer register
WDTR
W
0 1 1 1 1 1 1 1
byte
Watch dog timer data register
WDTDR
R
Undefined
00F5
Stop & sleep mode control register
SSCR
W
0 0 0 0 0 0 0 0
byte
00F6
Watch timer mode register
WTMR
R/W
0
-
-
0 0 0 0 0
byte, bit
00F7
PFD control register
PFDR
R/W
-
-
-
-
-
0 0 0
byte, bit
00F8
Port selection register 0
PSR0
W
0 0 0 0 0 0 0 0
byte
00F9
Port selection register 1
PSR1
W
-
-
-
-
0 0 0 0
byte
00FA
Reserved
00FB
Reserved
00FC
Pull-up selection register 0
PU0
W
0 0 0 0 0 0 0 0
byte
00FD
Pull-up selection register 1
PU1
W
0 0 0 0 0 0 0 0
byte
00FE
Pull-up selection register 4
PU4
W
0 0 0 0 0 0 0 0
byte
00FF
Reserved
0EE6
UART1 mode register
ASIMR1
R/W
0 0 0 0
-
0 0
-
byte, bit
0EE7
UART1 status register
ASISR1
R
-
-
-
-
-
0 0 0
byte
0EE8
UART1 Baud rate generator control register
BRGCR1
R/W
-
0 0 1 0 0 0 0
byte, bit
0EE9
UART1 Receive buffer register
RXR1
R
0 0 0 0 0 0 0 0
byte
UART1 Transmit shift register
TXR1
W
1 1 1 1 1 1 1 1
Address
Register Name
Symbol
R/W
Initial Value
Addressing
Mode
7
6
5
4
3
2
1
0
Table 8-1 Control Registers
The ‘byte’ means registers are controlled by only byte manipulation instruction. Do not use bit manipulation
instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers,
content of other seven bits are may varied to unwanted value.
1.
The ‘byte, bit’ means registers are controlled by both bit and byte manipulation instruction.
Caution) The R/W register except T1PDR and T3PDR are both can be byte and bit manipulated.
2.
*The mark of ‘-’ means this bit location is reserved.
3.
The UART1 control register ASIMR1,ASISR1, BRGCR1,RXR1 and TXR1 are located at EE6H ~ EE9H address.
These address must be accessed(read and written) by absolute addressing manipulation instruction.