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| 型號(hào)： | MC80C0208 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類(lèi)： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁(yè)數(shù)： | 109/128頁(yè) |
| 文件大?。?/td> | 1408K |
| 代理商： | MC80C0208 |
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Preliminary
MC80F0208/16/24
MAR. 2005 Ver 0.2
105
24. POWER FAIL PROCESSOR
The MC80F0208/16/24 has an on-chip power fail detection cir-
cuitry to immunize against power noise. A configuration register,
PFDR, can enable or disable the power fail detect circuitry.
Whenever V
DD
falls close to or below power fail voltage for
100ns, the power fail situation may reset or freeze MCU accord-
ing to PFDM bit of PFDR. Refer to “Figure 24-1 Power Fail Volt-
age Detector Register” on page 105.
In the in-circuit emulator, power fail function is not implemented
and user can not experiment with it. Therefore, after final devel-
opment of user program, this function may be experimented or
evaluated.
Note:
User can select power fail voltage level according to
PFS0, PFS1 bit of CONFIG register(703FH) at the FLASH
(MC80F0208/16/24) but must select the power fail voltage
level to define PFD option of "Mask Order & Verification
Sheet" at the mask chip(MC80C0208/16/24), because the
power fail voltage level of mask chip (MC80C0208/16/24) is
determined according to mask option.
Note:
If power fail voltage is selected to 2.4V or 2.7V on
below 3V operation, MCU is freezed at all the times.
Table 24-1 Power fail processor
Figure 24-1 Power Fail Voltage Detector Register
Power Fail Function
FLASH
MASK
Enable/Disable
PFDEN flag
PFDEN flag
Level Selection
PFS0 bit
PFS1 bit
Mask option
PFDM
7
-
6
-
5
-
4
-
3
-
2
1
0
PFDS
INITIAL VALUE: ---- -000
B
ADDRESS: 0F7
H
PFDR
R/W
R/W
R/W
PFDEN
PFD Operation Mode
0 : MCU will be frozen by power fail detection
1 : MCU will be reset by power fail detection
PFD Enable Bit
0: Power fail detection disable
1: Power fail detection enable
Power Fail Status
0: Normal operate
1: Set to “1” if power fail is detected
* Cautions :
Be sure to set bits 3 through 7 to “0”.
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