- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376153 > MC80C0208 (Electronic Theatre Controls, Inc.) 8-BIT SINGLE-CHIP MICROCONTROLLERS PDF資料下載
參數(shù)資料
| 型號(hào)： | MC80C0208 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁(yè)數(shù)： | 101/128頁(yè) |
| 文件大?。?/td> | 1408K |
| 代理商： | MC80C0208 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)當(dāng)前第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)
Preliminary
MC80F0208/16/24
MAR. 2005 Ver 0.2
97
The reset should not be activated before V
DD
is restored to its
normal operating level, and must be held active long enough to
allow the oscillator to restart and stabilize.
Note:
After STOP instruction, at least two or more NOP in-
struction should be written.
Ex)
LDM CKCTLR,#0FH ;more than 20ms
LDM SSCR,#5AH
STOP
NOP ;for stabilization time
NOP ;for stabilization time
In the STOP operation, the dissipation of the power associated
with the oscillator and the internal hardware is lowered; however,
the power dissipation associated with the pin interface (depend-
ing on the external circuitry and program) is not directly deter-
mined by the hardware operation of the STOP feature. This point
should be little current flows when the input level is stable at the
power voltage level (V
DD
/V
SS
); however, when the input level
gets higher than the power voltage level (by approximately 0.3 to
0.5V), a current begins to flow. Therefore, if cutting off the out-
put transistor at an I/O port puts the pin signal into the high-im-
pedance state, a current flow across the ports input transistor,
requiring to fix the level by pull-up or other means.
Release the STOP mode
The source for exit from STOP mode is hardware reset, external
interrupt, Timer(EC0,1), Watch Timer, WDT, SIO or UART. Re-
set re-defines all the Control registers but does not change the on-
chip RAM. External interrupts allow both on-chip RAM and
Control registers to retain their values.
If I-flag = 1, the normal interrupt response takes place. If I-flag =
0, the chip will resume execution starting with the instruction fol-
lowing the STOP instruction. It will not vector to interrupt service
routine. (refer to Figure 21-4)
When exit from Stop mode by external interrupt, enough oscilla-
tion stabilization time is required to normal operation. Figure 21-
5 shows the timing diagram. When released from the Stop mode,
the Basic interval timer is activated on wake-up. It is increased
from 00
H
until FF
H
. The count overflow is set to start normal op-
Peripheral
STOP Mode
SLEEP Mode
CPU
Stop
Stop
RAM
Retain
Retain
Basic Interval Timer
Halted
Operates Continuously
Watchdog Timer
Stop (Only operates in RC-WDT mode)
Stop
Watch Timer
Stop
Stop
Timer/Counter
Halted(Only when the event counter mode is
enabled, timer operates normally)
Operates Continuously
Buzzer, ADC
Stop
Stop
SIO
Only operate with external clock
Only operate with external clock
UART
Only operate with external clock
Only operate with external clock
Oscillator
Stop(X
IN
=L, X
OUT
=H)
Oscillation
Sub Oscillator
Oscillation
Oscillation
I/O Ports
Retain
Retain
Control Registers
Retain
Retain
Internal Circuit
Stop mode
Sleep mode
Prescaler
Retain
Active
Address Data Bus
Retain
Retain
Release Source
Reset, Timer(EC0,1), SIO, UART0(using
ACLK0), UART1(using ACLK1)
Watch Timer( RC-WDT mode),
Watchdog Timer( RC-WDT mode),
External Interrupt
Reset, All Interrupts
Table 21-1 Peripheral Operation During Power Saving Mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC80C0208K | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| MC80C0208Q | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| MC80C0216 | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| MC80C0216K | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| MC80C0216Q | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC80C0208K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT SINGLE-CHIP MICROCONTROLLERS |
| MC80C0208Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT SINGLE-CHIP MICROCONTROLLERS |
| MC80C0216 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT SINGLE-CHIP MICROCONTROLLERS |
| MC80C0216K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT SINGLE-CHIP MICROCONTROLLERS |
| MC80C0216Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT SINGLE-CHIP MICROCONTROLLERS |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。