- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄45250 > MC7457VG867NC (FREESCALE SEMICONDUCTOR INC) 32-BIT, 867 MHz, RISC PROCESSOR, CBGA483 PDF資料下載
參數(shù)資料
| 型號(hào)： | MC7457VG867NC |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 867 MHz, RISC PROCESSOR, CBGA483 |
| 封裝： | 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, CERAMIC, BGA-483 |
| 文件頁(yè)數(shù)： | 37/73頁(yè) |
| 文件大?。?/td> | 1715K |
| 代理商： | MC7457VG867NC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)當(dāng)前第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
42
Freescale Semiconductor
Pinout Listings
TDI
E4
High
Input
BVSEL
7
TDO
H1
High
Output
BVSEL
TEA
T1
Low
Input
BVSEL
TEST[0:5]
B10, H6, H10, D8, F9, F8
—
Input
BVSEL
13
TEST[6]
A9
—
Input
BVSEL
10
TMS
K4
High
Input
BVSEL
7
TRST
C1
Low
Input
BVSEL
7, 16
TS
P5
Low
I/O
BVSEL
3
TSIZ[0:2]
L1,H3,D1
High
Output
BVSEL
TT[0:4]
F1, F4, K8, A5, E1
High
I/O
BVSEL
L2
Low
Output
BVSEL
VDD
J9, J11, J13, J15, K10, K12, K14, L9, L11, L13, L15,
M10, M12, M14, N9, N11, N13, N15, P10, P12, P14
——
N/A
VDD_SENSE[0:1]
G11, J8
—
N/A
17
Notes:
1. OVDD supplies power to the processor bus, JTAG, and all control signals except the L3 cache controls (L3CTL[0:1]); GVDD
supplies power to the L3 cache interface (L3ADDR[0:17], L3DATA[0:63], L3DP[0:7], L3_ECHO_CLK[0:3], and L3_CLK[0:1])
and the L3 control signals L3_CNTL[0:1]; and VDD supplies power to the processor core and the PLL (after filtering to become
2. Unused address pins must be pulled down to GND.
3. These pins require weak pull-up resistors (for example, 4.7 k
Ω) to maintain the control signals in the negated state after they
have been actively negated and released by the MPC7457 and other bus masters.
4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going
high.
5. This signal must be negated during reset, by pull up to OVDD or negation by HRESET (inverse of HRESET), to ensure
proper operation.
6. See Table 3 for bus voltage configuration information. If used, pull-down resistors should be less than 250
Ω.
7. Internal pull up on die.
8. Ignored in 60x bus mode.
9. These signals must be pulled down to GND if unused or if the MPC7457 is in 60x bus mode.
10.These input signals for factory use only and must be pulled down to GND for normal machine operation.
11.Power must be supplied to GVDD, even when the L3 interface is disabled or unused.
12.This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect performance.
13.These input signals are for factory use only and must be pulled up to OVDD for normal machine operation.
14.These signals are for factory use only and must be left unconnected for normal machine operation.
15.This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
16.This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.
17.These pins are internally connected to VDD. They are intended to allow an external device to detect the core voltage level
present at the processor core. If unused, they must be connected directly to VDD or left unconnected.
Table 17. Pinout Listing for the MPC7457, 483 CBGA Package (continued)
Signal Name
Pin Number
Active
I/O
I/F Select 1
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC7457RX1267LC | 32-BIT, 1267 MHz, RISC PROCESSOR, CBGA483 |
| MC7457VG733NC | 32-BIT, 733 MHz, RISC PROCESSOR, CBGA483 |
| MC74ACT125DR2 | ACT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14 |
| MC74AC125DR2 | AC SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14 |
| MC74ACT125DTR2 | ACT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC74A5-33SNTR | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| MC74A5-50T | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| MC74AC00 | 制造商:ONSEMI 制造商全稱(chēng):ON Semiconductor 功能描述:QUAD 2-INPUT NAND GATE |
| MC74AC00D | 功能描述:邏輯門(mén) 2-6V Quad 2-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線(xiàn)路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74AC00DG | 功能描述:邏輯門(mén) 2-6V Quad 2-Input NAND RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線(xiàn)路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。