參數(shù)資料
型號： MC7457VG867NC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 867 MHz, RISC PROCESSOR, CBGA483
封裝： 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, CERAMIC, BGA-483
文件頁數(shù)： 19/73頁
文件大?。?/td> 1715K
代理商： MC7457VG867NC
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
26
Freescale Semiconductor
Electrical and Thermal Characteristics
window at the internal receiving latches. This delayed clock is used to capture the data into these latches
which comprise the receive FIFO. This clock is asynchronous to all other processor clocks. This latched
data is subsequently read out of the FIFO synchronously to the processor clock. The time between writing
and reading the data is set by the using the sample point settings defined in the L3CR register.
Table 13 provides the L3 bus interface AC timing specifications for the configuration as shown in
Figure 9, assuming the timing relationships shown in Figure 10 and the loading shown in Figure 8.
Table 13. L3 Bus Interface AC Timing Specifications for MSUG2
At recommended operating conditions. See Table 4.
Parameter
Symbol
Device Revision (L3 I/O Voltage) 9
Unit
Notes
Rev 1.1. (All I/O Modes)
Rev 1.2 (1.5-V I/O Mode)
Rev 1.2
(1.8-, 2.5-V I/O Modes)
Min
Max
Min
Max
L3_CLK rise and fall time
tL3CR, tL3CF
—
0.75
—
0.75
ns
1
Setup times: Data and parity
tL3DVEH,
tL3DVEL
(– tL3CLK/4)
+ 0.90
—(– tL3CLK/4)
+ 0.70
—
ns
2, 3, 4
Input hold times: Data and parity
tL3DXEH,
tL3DXEL
(tL3CLK/4)
+ 0.85
—(tL3CLK/4)
+ 0.70
—ns
2, 4
Valid times: Data and parity
tL3CHDV,
tL3CLDV
—(– tL3CLK/4)
+ 0.60
—(– tL3CLK/4)
+ 0.50
ns
5, 6,
7, 8
Valid times: All other outputs
tL3CHOV
—(tL3CLK/4)
+ 0.65
—(tL3CLK/4)
+ 0.65
ns
5, 7, 8
Output hold times: Data and parity
tL3CHDX,
tL3CLDX,
(tL3CLK/4)
– 0.60
—(tL3CLK/4)
– 0.50
—ns
5, 6,
7, 8
Output hold times: All other outputs
tL3CHOX
(tL3CLK/4)
– 0.50
—(tL3CLK/4)
– 0.50
—
ns
5, 7, 8
L3_CLK to high impedance: Data
and parity
tL3CLDZ
—(– tL3CLK/4)
+ 0.60
—(– tL3CLK/4)
+ 0.60
ns
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