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參數(shù)資料
| 型號： | MC7455ARX1000LG |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA483 |
| 封裝： | 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483 |
| 文件頁數(shù)： | 5/76頁 |
| 文件大?。?/td> | 1520K |
| 代理商： | MC7455ARX1000LG |
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MOTOROLA
MPC7455 RISC Microprocessor Hardware Specifications
13
Electrical and Thermal Characteristics
Table 5 provides the package thermal characteristics for the MPC7455.
Table 6 provides the DC electrical characteristics for the MPC7455.
Table 5. Package Thermal Characteristics 6
Characteristic
Symbol
Value
Unit
Notes
MPC7445
MPC7455
Junction-to-ambient thermal resistance, natural
convection
RθJA
22
20
°C/W
1, 2
Junction-to-ambient thermal resistance, natural
convection, four-layer (2s2p) board
RθJMA
14
°C/W
1, 3
Junction-to-ambient thermal resistance, 200 ft/min
airflow, single-layer (1s) board
RθJMA
16
15
°C/W
1, 3
Junction-to-ambient thermal resistance, 200 ft/min
airflow, four-layer (2s2p) board
RθJMA
11
°C/W
1, 3
Junction-to-board thermal resistance
RθJB
6
°C/W
4
Junction-to-case thermal resistance
RθJC
<0.1
°C/W
5
Notes:
1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board
thermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1) with the calculated case temperature. The actual value of RθJC for the part is less
than 0.1°C/W.
6. Refer to Section 1.9.8, “Thermal Management Information,” for more details about thermal management.
Table 6. DC Electrical Specifications
At recommended operating conditions. See Table 4.
Characteristic
Nominal
Bus
Voltage 1
Symbol
Min
Max
Unit
Notes
Input high voltage
(all inputs except SYSCLK)
1.5
VIH
GVDD × 0.65
GVDD + 0.3
V
6
1.8
VIH
OVDD/GVDD × 0.65 OVDD/GVDD + 0.3
V
2.5
VIH
1.7
OVDD/GVDD + 0.3
V
Input low voltage
(all inputs except SYSCLK)
1.5
VIL
–0.3
GVDD × 0.35
V
6
1.8
VIL
–0.3
OVDD/GVDD × 0.35
V
2.5
VIL
–0.3
0.7
V
SYSCLK input high voltage
—
CVIH
1.4
OVDD + 0.3
V
SYSCLK input low voltage
—
CVIL
–0.3
0.4
V
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