參數(shù)資料
型號(hào)： MC7455ARX1000LG
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA483
封裝： 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483
文件頁(yè)數(shù)： 24/76頁(yè)
文件大?。?/td> 1520K
代理商： MC7455ARX1000LG
30
MPC7455 RISC Microprocessor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Figure 12 shows the L3 bus timing diagrams for the MPC7455 interfaced to PB2 or late write SRAMs.
Figure 12. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs
1.5.2.5
IEEE 1149.1 AC Timing Specifications
Table 14 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 14 through
Figure 17.
Table 14. JTAG AC Timing Specifications (Independent of SYSCLK) 1
At recommended operating conditions. See Table 4.
Parameter
Symbol
Min
Max
Unit
Notes
TCK frequency of operation
fTCLK
033.3
MHz
TCK cycle time
t TCLK
30
—
ns
TCK clock pulse width measured at 1.4 V
tJHJL
15
—
ns
TCK rise and fall times
tJR and tJF
02
ns
TRST assert time
tTRST
25
—
ns
2
Input setup times:
Boundary-scan data
TMS, TDI
tDVJH
tIVJH
4
0
—
ns
3
Input hold times:
Boundary-scan data
TMS, TDI
tDXJH
tIXJH
20
25
—
ns
3
L3_ECHO_CLK[0,2]
L3 Data and Data
VM
VM = Midpoint Voltage (GVDD/2)
tL3DVEH
tL3DXEH
Parity Inputs
L3_CLK[0,1]
ADDR, L3_CNTL
VM
tL3CHOV
tL3CHOX
VM
L3DATA WRITE
tL3CHDZ
Outputs
Inputs
L3_ECHO_CLK[1,3]
tL3CHDV
tL3CHDX
tL3CHOZ
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