參數(shù)資料
型號: MC705JJ7CDWE
廠商: Freescale Semiconductor
文件頁數(shù): 93/164頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 224B RAM 20-SOIC
標(biāo)準(zhǔn)包裝: 38
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設(shè)備: POR,溫度傳感器,WDT
輸入/輸出數(shù): 14
程序存儲器容量: 6KB(6K x 8)
程序存儲器類型: OTP
RAM 容量: 224 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 管件
Interrupts
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
34
Freescale Semiconductor
4.3 Interrupt Processing
To begin servicing an interrupt, the CPU does these actions:
Stores the CPU registers on the stack in the order shown in Figure 4-1
Sets the I bit in the condition code register to prevent further interrupts
Loads the program counter with the contents of the appropriate interrupt vector locations as shown
The return-from-interrupt (RTI) instruction causes the CPU to recover its register contents from the stack
as shown in Figure 4-1. The sequence of events caused by an interrupt is shown in the flowchart in
$0020
Bottom of RAM
$0021
$00BE
$00BF
$00C0
Bottom of Stack
$00C1
$00C2
Unstacking
Order
?
n
Condition Code Register
5
1
n+1
Accumulator
4
2
n+2
Index Register
3
n+3
Program Counter (High Byte)
2
4
n+4
Program Counter (Low Byte)
1
5
Stacking
Order
$00FD
$00FE
$00FF
Top of Stack (RAM)
Figure 4-1. Interrupt Stacking Order
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參數(shù)描述
MC705JJ7CDWE 制造商:Freescale Semiconductor 功能描述:8-Bit Microcontroller IC
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