參數(shù)資料
型號(hào)： MC705JJ7CDWE
廠商： Freescale Semiconductor
文件頁數(shù)： 106/164頁
文件大小： 0K
描述： IC MCU 8BIT 224B RAM 20-SOIC
標(biāo)準(zhǔn)包裝： 38
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 14
程序存儲(chǔ)器容量： 6KB（6K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
包裝： 管件
Resets
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
46
Freescale Semiconductor
The LVR reset function can be enabled or disabled by programming the LVREN bit in the MOR.
NOTE
The LVR is intended for applications where the VDD supply voltage
normally operates above 4.5 volts.
5.4.4 Illegal Address Reset
An opcode fetch (execution of an instruction) at an address that is not in the EPROM (locations
$0700–$1FFF) or the RAM (locations $0020–$00FF) generates an illegal address reset. The illegal
address reset will assert the pulldown device to pull the RESET pin low for three to four cycles of the
internal bus.
5.5 Reset States
This subsection describe how the various resets initialize the MCU.
5.5.1 CPU
A reset has these effects on the CPU:
Loads the stack pointer with $FF
Sets the I bit in the condition code register, inhibiting interrupts
Loads the program counter with the user-defined reset vector from locations $1FFE and $1FFF
Clears the stop latch, enabling the CPU clock
Clears the wait latch, bringing the CPU out of the wait mode
5.5.2 I/O Registers
A reset has these effects on input/output (I/O) registers:
Clears bits in data direction registers configuring pins as inputs:
–
DDRA5–DDRA0 in DDRA for port A
–
DDRB7–DDRB0 in DDRB for port B
–
DDRC7–DDRC0 in DDRC for port C(1)
Clears bits in pulldown inhibit registers to enable pulldown devices:
–
PDIA5–PDIA0 in PDRA for port A
–
PDIB7–PDIB0 in PDRB for port B
–
PDICH and PDICL in PDRA for port C(1)
Has no effect on port A, B, or C(1) data registers
Sets the IRQE bit in the interrupt status and control register (ISCR)
5.5.3 Core Timer
A reset has these effects on the core timer:
Clears the core timer counter register (CTCR)
Clears the core timer interrupt flag and enable bits in the core timer status and control register
(CTSCR)
Sets the real-time interrupt (RTI) rate selection bits (RT0 and RT1) such that the device will start
with the longest real-time interrupt and longest COP timeout delays
1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices
相關(guān)PDF資料
PDF描述
VI-B1H-IY-F4 CONVERTER MOD DC/DC 52V 50W
VE-B43-IX-B1 CONVERTER MOD DC/DC 24V 75W
AD724JRZ-RL IC ENCODER RGB TO NTSC 16SOIC TR
VE-B42-IX-B1 CONVERTER MOD DC/DC 15V 75W
VI-B1F-IY-F3 CONVERTER MOD DC/DC 72V 50W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC705JJ7CDWE 制造商:Freescale Semiconductor 功能描述:8-Bit Microcontroller IC
MC705JP7CPE 功能描述:8位微控制器 -MCU 8B MCU 224 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
MC705JP7CPE 制造商:Freescale Semiconductor 功能描述:IC 8BIT MCU 68HC05 2.1MHZ DIP-28
MC705K1CP 制造商:Motorola Inc 功能描述:16 PIN DIP INTEGRATED CIRCUIT
MC705L16CFUE 功能描述:8位微控制器 -MCU 8B MCU W/ EPROM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*