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參數(shù)資料
| 型號： | MC68HSC05P1AP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 94/124頁 |
| 文件大?。?/td> | 623K |
| 代理商： | MC68HSC05P1AP |
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16-Bit Timer
Input Capture
MC68HC05P1A — Rev. 3.0
General Release Specification
MOTOROLA
16-Bit Timer
71
NON-DISCLOSURE
AGREEMENT
REQUIRED
8.5 Input Capture
Two 8-bit read-only registers (ICRH and ICRL) make up the 16-bit input
capture. They are used to latch the value of the free-running counter
after a defined transition is sensed by the input capture edge detector.
(Note that the input capture edge detector contains a Schmitt trigger to
improve noise immunity.) The edge that triggers the counter transfer is
defined by the input edge bit (IEDG) in register TCR. Reset does not
affect the contents of the input capture registers. See Figure 8-2.
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the PH2 clock preceding
the external transition (see Figure 8-10). This delay is required for
internal synchronization. Resolution is affected by the prescaler,
allowing the free-running counter to increment once every four PH2
clock cycles.
The contents of the free-running counter are transferred to the input
capture registers on each proper signal transition regardless of the state
of the input capture flag bit (ICF) in register TSR. The input capture
ICRH
$0014
Bit 7
654321
Bit 0
Read:
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
Write:
Reset:
Unaffected by Reset
= Unimplemented
ICRL
$0015
Bit 7
654321
Bit 0
Read:
ICRL7
ICRL6
ICRL5
ICRL4
ICRL3
ICRL2
ICRL1
ICRL0
Write:
Reset:
Unaffected by Reset
= Unimplemented
Figure 8-9. Input Compare Registers (ICRH/ICRL)
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