參數(shù)資料
型號(hào)： MC68HSC05P1AP
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDIP28
封裝： PLASTIC, DIP-28
文件頁(yè)數(shù)： 42/124頁(yè)
文件大小： 623K
代理商： MC68HSC05P1AP
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NON-DISCLOSURE
AGREEMENT
REQUIRED
General Description
General Release Specification
MC68HC05P1A — Rev. 3.0
24
General Description
MOTOROLA
1.6.5 TCMP
This pin is the output from the 16-bit timer’s output compare function. It
is low after reset. Refer to Section 8. 16-Bit Timer.
1.6.6 IRQ (Maskable Interrupt Request)
This input pin drives the asynchronous interrupt function of the MCU.
The MCU will complete the current instruction being executed before it
responds to the IRQ interrupt request. When IRQ is driven low, the event
is latched internally to signify an interrupt has been requested. When the
MCU completes its current instruction, the interrupt latch is tested. If the
interrupt latch is set and the interrupt mask bit (I bit) in the condition code
register is clear, the MCU will begin the interrupt sequence.
Depending on the mask option selected, the IRQ pin will trigger this
interrupt on either a negative going edge at the IRQ pin and/or while the
IRQ pin is held in the low state. In either case, the IRQ pin must be held
low for at least one tILIH time period. The IRQ input requires an external
resistor connected to VDD for wired-OR operation. If the IRQ pin is not
used, it must be tied to the VDD supply. The IRQ pin contains an internal
Schmitt trigger as part of its input circuitry to improve noise immunity.
NOTE:
Each of the port A I/O pins may be connected as an OR function with the
IRQ interrupt function by a mask option. This capability allows keyboard
scan applications where the transitions or levels on the I/O pins will
behave the same as the IRQ pin. The edge or level sensitivity selected
by a separate mask option for the IRQ pin also applies to the I/O pins
OR’ed to create the IRQ signal.
NOTE:
If the voltage level applied to the IRQ pin exceeds 1.5 VDD, it may affect
the MCU’s mode of operation. See Section 6. Operating Modes.
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