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參數(shù)資料
| 型號： | MC68HSC05P1AP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 53/124頁 |
| 文件大?。?/td> | 623K |
| 代理商： | MC68HSC05P1AP |
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NON-DISCLOSURE
AGREEMENT
REQUIRED
CPU Core
General Release Specification
MC68HC05P1A — Rev. 3.0
34
CPU Core
MOTOROLA
and loses the previously stored information. A subroutine call occupies
two locations on the stack; an interrupt uses five locations.
3.3.4 Program Counter
The program counter (PC) is a 13-bit register that contains the address
of the next byte to be fetched. Because addresses are often 16-bit
values, the program counter may be thought of as having three
additional upper bits that are always zeros.
Normally, the address in the program counter increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
3.3.5 Condition Code Register
The condition code register (CCR) is a 5-bit register in which the H, N,
Z, and C bits are used to indicate the results of the instruction just
executed, and the I bit is used to enable or disable interrupts. These bits
can be individually tested by a program, and specific actions can be
taken as a result of their state. Consider the condition code register as
having three additional upper bits that are always ones.
H — Half Carry
This bit is set during ADD and ADC operations to indicate that a carry
occurred between bits 3 and 4.
12
7
50
0000011
SP
15
12
0
000
PC
74
3
2
1
0
111
H
I
N
Z
C
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