參數(shù)資料
型號(hào): MC68HRC705KJ1CP
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 74/108頁(yè)
文件大?。?/td> 0K
描述: IC MCU 1.2K 4MHZ OTP 16-DIP
標(biāo)準(zhǔn)包裝: 25
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 10
程序存儲(chǔ)器容量: 1.2KB(1.2K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-DIP(0.300",7.62mm)
包裝: 管件
Parallel I/O Ports (PORTS)
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
68
Freescale Semiconductor
7.3.3 Pulldown Register B
Pulldown register B inhibits the pulldown devices on port B pins programmed as inputs.
NOTE
If the SWPDI bit in the mask option register is programmed to logic 1, reset
initializes all port B pins as inputs with disabled pulldown devices.
PDIB[3:2] — Pulldown Inhibit B Bits
PDIB[3:2] disable the port B pulldown devices. Reset clears PDIB[3:2].
1 = Corresponding port B pulldown device disabled
0 = Corresponding port B pulldown device not disabled
Table 7-2. Port B Pin Operation
Data Direction Bit
I/O Pin Mode
Accesses to Data Bit
Read
Write
0
Input, high-impedance
Pin
Latch(1)
1. Writing affects the data register, but does not affect input.
1
Output
Latch
Address:
$0011
Bit 7
654321
Bit 0
Read:
Write:
See Note
PDIB3
PDIB2
See Note
Reset:
000000
= Unimplemented
Note:
These pulldown devices are permanently enabled when PB5, PB4, PB1 and PB0 are con-
figured as inputs.
Figure 7-9. Pulldown Register B (PDRB)
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