參數(shù)資料
型號(hào)： MC68HRC705KJ1CP
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 31/108頁(yè)
文件大?。?/td> 0K
描述： IC MCU 1.2K 4MHZ OTP 16-DIP
標(biāo)準(zhǔn)包裝： 25
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 4MHz
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 10
程序存儲(chǔ)器容量： 1.2KB（1.2K x 8）
程序存儲(chǔ)器類(lèi)型： OTP
RAM 容量： 64 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 16-DIP（0.300"，7.62mm）
包裝： 管件
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
29
Chapter 3
Computer Operating Properly Module (COP)
3.1 Introduction
The computer operating properly (COP) watchdog resets the MCU in case of software failure. Software
that is operating properly periodically services the COP watchdog and prevents COP reset. The COP
watchdog function is programmable by the COPEN bit in the mask option register.
3.2 Features
The computer operating properly module (COP) includes these features:
Protection from runaway software
Wait mode and halt mode operations
3.3 Operation
Operation of the COP module is discussed here.
3.3.1 COP Watchdog Timeout
Four counter stages at the end of the timer make up the COP watchdog. The COP resets the MCU if the
timeout period occurs before the COP watchdog timer is cleared by application software and the IRQ/VPP
pin voltage is between VSS and VDD. Periodically clearing the counter starts a new timeout period and
prevents COP reset. A COP watchdog timeout indicates that the software is not executing instructions in
the correct sequence.
NOTE
The internal clock drives the COP watchdog. Therefore, the COP watchdog
cannot generate a reset for errors that cause the internal clock to stop.
The COP watchdog depends on a power supply voltage at or above a
minimum specification and is not guaranteed to protect against brownout.
3.3.2 COP Watchdog Timeout Period
The COP watchdog timer function is implemented by dividing the output of the real-time interrupt circuit
(RTI) by eight. The RTI select bits in the timer status and control register control RTI output, and the
selected output drives the COP watchdog. (See timer status and control register in Chapter 9
NOTE
The minimum COP timeout period is seven times the RTI period. The COP
is cleared asynchronously with the value in the RTI divider; hence, the COP
timeout period will vary between 7x and 8x the RTI period.
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