參數(shù)資料
型號: MC68HRC705KJ1CP
廠商: Freescale Semiconductor
文件頁數(shù): 47/108頁
文件大小: 0K
描述: IC MCU 1.2K 4MHZ OTP 16-DIP
標(biāo)準(zhǔn)包裝: 25
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 10
程序存儲器容量: 1.2KB(1.2K x 8)
程序存儲器類型: OTP
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-DIP(0.300",7.62mm)
包裝: 管件
Instruction Set
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
43
4.6.3 Instruction Set Summary
Table 4-6. Instruction Set Summary (Sheet 1 of 6)
Source
Form
Operation
Description
Effect
on CCR
Addre
s
M
ode
Op
code
O
p
er
and
Cycles
HIN Z C
ADC #opr
ADC opr
ADC opr,X
ADC ,X
Add with Carry
A
← (A) + (M) + (C)
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
ADD #opr
ADD opr
ADD opr,X
ADD ,X
Add without Carry
A
← (A) + (M)
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
AND #opr
AND opr
AND opr,X
AND ,X
Logical AND
A
← (A) ∧ (M)
— —
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
Arithmetic Shift Left (Same as LSL)
— —
DIR
INH
IX1
IX
38
48
58
68
78
dd
ff
5
3
6
5
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
Arithmetic Shift Right
— —
DIR
INH
IX1
IX
37
47
57
67
77
dd
ff
5
3
6
5
BCC rel
Branch if Carry Bit Clear
PC
← (PC) + 2 + rel ? C = 0
— ————
REL
24
rr
3
BCLR n opr
Clear Bit n
Mn
← 0
— ————
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
5
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC
← (PC) + 2 + rel ? C = 1
— ————
REL
25
rr
3
BEQ rel
Branch if Equal
PC
← (PC) + 2 + rel ? Z = 1
— ————
REL
27
rr
3
BHCC rel
Branch if Half-Carry Bit Clear
PC
← (PC) + 2 + rel ? H = 0
— ————
REL
28
rr
3
BHCS rel
Branch if Half-Carry Bit Set
PC
← (PC) + 2 + rel ? H = 1
— ————
REL
29
rr
3
BHI rel
Branch if Higher
PC
← (PC) + 2 + rel ? C ∨ Z = 0 — ————
REL
22
rr
3
BHS rel
Branch if Higher or Same
PC
← (PC) + 2 + rel ? C = 0
— ————
REL
24
rr
3
BIH rel
Branch if IRQ Pin High
PC
← (PC) + 2 + rel ? IRQ = 1 — ————
REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC
← (PC) + 2 + rel ? IRQ = 0 — ————
REL
2E
rr
3
C
b0
b7
0
b0
b7
C
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