參數(shù)資料
型號: MC68HLC705KJ1CDWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16
封裝: SOIC-16
文件頁數(shù): 128/144頁
文件大小: 1377K
代理商: MC68HLC705KJ1CDWR2
Technical Data
MC68HC705KJ1 — Rev. 2.0
84
Parallel I/O Ports
MOTOROLA
Parallel I/O Ports
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 7-4 shows the I/O logic of port A.
Figure 7-4. Port A I/O Circuitry
Writing a logic 1 to a DDRA bit enables the output buffer for the
corresponding port A pin; a logic 0 disables the output buffer.
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data
latch. When bit DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 7-1 summarizes the operation
of the port A pins.
READ DDRA
WRITE DDRA
RESET
WRITE PORTA
READ PORTA
PAx
INTERNAL
D
AT
A
B
U
S
DDRAx
PAx
PDRAx
SWPDI
100-
A
PULLDOWN
(PA0–PA3 TO
IRQ MODULE)
WRITE PDRA
10-mA SINK CAPABILITY
(PINS PA4–PA7 ONLY)
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