參數(shù)資料
型號: MC68HLC705KJ1CDWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16
封裝: SOIC-16
文件頁數(shù): 119/144頁
文件大?。?/td> 1377K
代理商: MC68HLC705KJ1CDWR2
Technical Data
MC68HC705KJ1 — Rev. 2.0
76
Low-Power Modes
MOTOROLA
Low-Power Modes
6.4.1.2 WAIT
The WAIT instruction disables the CPU clock.
After exiting wait mode, the CPU clock and all enabled peripheral clocks
immediately begin running.
6.4.2 CPU
Effects of STOP and WAIT on the CPU are discussed here.
6.4.2.1 STOP
The STOP instruction:
Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
After exit from stop mode by external interrupt, the I bit remains clear.
After exit from stop mode by reset, the I bit is set.
6.4.2.2 WAIT
The WAIT instruction:
Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts
Disables the CPU clock
After exit from wait mode by interrupt, the I bit remains clear.
After exit from wait mode by reset, the I bit is set.
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