參數(shù)資料
型號: MC68HLC705KJ1CDWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16
封裝: SOIC-16
文件頁數(shù): 117/144頁
文件大小: 1377K
代理商: MC68HLC705KJ1CDWR2
Technical Data
MC68HC705KJ1 — Rev. 2.0
74
Low-Power Modes
MOTOROLA
Low-Power Modes
6.2 Introduction
The MCU can enter the following low-power standby modes:
Stop mode — The STOP instruction puts the MCU in its lowest
power-consumption mode.
Wait mode — The WAIT instruction puts the MCU in an
intermediate power-consumption mode.
Halt mode — Halt mode is identical to wait mode, except that an
oscillator stabilization delay of 1 to 4064 internal clock cycles
occurs when the MCU exits halt mode. The stop-to-wait
conversion bit, SWAIT, in the mask option register, enables halt
mode.
Enabling halt mode prevents the computer operating properly
(COP) watchdog from being inadvertently turned off by a STOP
instruction.
Data-retention mode — In data-retention mode, the MCU retains
RAM contents and CPU register contents at VDD voltages as low
as 2.0 Vdc. The data-retention feature allows the MCU to remain
in a low power-consumption state during which it retains data, but
the CPU cannot execute instructions.
6.3 Exiting Stop and Wait Modes
The following events bring the MCU out of stop mode and load the
program counter with the reset vector or with an interrupt vector:
Exiting Stop Mode
starts the CPU clock, and loads the program counter with the
contents of locations $07FE and $07FF.
External interrupt — A high-to-low transition on the IRQ/VPP pin or
a low-to-high transition on an enabled port A external interrupt pin
starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
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