參數(shù)資料
型號： MC68HLC705KJ1C
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP16
封裝： PLASTIC, DIP-16
文件頁數(shù)： 136/144頁
文件大小： 1575K
代理商： MC68HLC705KJ1C
Parallel I/O Ports
Port B
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 3.0
Technical Data
MOTOROLA
Parallel I/O Ports
91
7.4.3 Pulldown Register B
Pulldown register B inhibits the pulldown devices on port B pins
programmed as inputs.
NOTE:
If the SWPDI bit in the mask option register is programmed to logic 1,
reset initializes all port B pins as inputs with disabled pulldown devices.
PDIB[3:2] — Pulldown Inhibit B Bits
PDIB[3:2] disable the port B pulldown devices. Reset clears
PDIB[3:2].
1 = Corresponding port B pulldown device disabled
0 = Corresponding port B pulldown device not disabled
Address:
$0011
Bit 7
6
54321
Bit 0
Read:
Write:
See Note
PDIB3
PDIB2
See Note
Reset:
000000
= Unimplemented
Note:
These pulldown devices are permanently enabled when PB5, PB4, PB1 and PB0 are
configured as inputs.
Figure 7-9. Pulldown Register B (PDRB)
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