參數(shù)資料
型號: MC68HLC705KJ1C
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 125/144頁
文件大?。?/td> 1575K
代理商: MC68HLC705KJ1C
Low-Power Modes
Data-Retention Mode
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 3.0
Technical Data
MOTOROLA
Low-Power Modes
81
6.5 Data-Retention Mode
In data-retention mode, the MCU retains RAM contents and CPU
register contents at VDD voltages as low as 2.0 Vdc. The data-retention
feature allows the MCU to remain in a low power-consumption state
during which it retains data, but the CPU cannot execute instructions.
To put the MCU in data-retention mode:
1. Drive the RESET pin to logic 0.
2. Lower the VDD voltage. The RESET pin must remain low
continuously during data-retention mode.
To take the MCU out of data-retention mode:
1. Return VDD to normal operating voltage.
2. Return the RESET pin to logic 1.
6.6 Timing
Figure 6-1. Stop Mode Recovery Timing
tILIH
OSCILLATOR STABILIZATION DELAY(5)
OSC
tRL
RESET
IRQ/VPP
INTERNAL
CLOCK
INTERNAL
ADDRESS
Notes:
1. Internal clocking from OSC1 pin
2. Edge-triggered external interrupt mask option
3. Edge- and level-triggered external interrupt mask option
4. Reset vector shown as example
RESET OR INTERRUPT
VECTOR FETCH
$07FE
$07FF
(NOTE 4)
BUS
(NOTE 3)
(NOTE 2)
(NOTE 1)
5. 4064 cycles or 128 cycles, depending on state of SOSCD bit in MOR
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