參數(shù)資料
型號: MC68HLC705KJ1C
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 135/144頁
文件大?。?/td> 1575K
代理商: MC68HLC705KJ1C
Technical Data
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 3.0
90
Parallel I/O Ports
MOTOROLA
Parallel I/O Ports
Figure 7-8. Port B I/O Circuitry
Writing a logic 1 to a DDRB bit enables the output buffer for the
corresponding port B pin; a logic 0 disables the output buffer.
When bit DDRBx is a logic 1, reading address $0001 reads the PBx data
latch. When bit DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 7-2 summarizes the operation
of the port B pins.
Table 7-2. Port B Pin Operation
Data Direction Bit
I/O Pin Mode
Accesses to Data Bit
Read
Write
0
Input, high-impedance
Pin
Latch(1)
1. Writing affects the data register, but does not affect input.
1
Output
Latch
READ DDRB
WRITE DDRB
RESET
WRITE PORTB
READ PORTB
PBx
IN
TE
RNA
LD
A
TA
B
U
S
DDRBx
PBx
PDRBx
SWPDI
100-
A
PULLDOWN
WRITE PDRB
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